Solid-state imaging apparatus, method for manufacturing solid-state imaging apparatus, and electronic equipment equipped with solid-state imaging apparatus
Provided are a solid-state imaging apparatus, a method for manufacturing a solid-state imaging apparatus, and an electronic apparatus equipped with a solid-state imaging apparatus that can reduce the size of a semiconductor chip in such a way that one semiconductor substrate having a logic circuit controls two sensors. Provided is a solid-state imaging apparatus including a first sensor, a first semiconductor substrate having a memory, a second semiconductor substrate having a logic circuit, and a second sensor, in which the first sensor, the first semiconductor substrate, the second semiconductor substrate, and the second sensor are arranged in this order.
1. A solid-state imaging apparatus, comprising:
a first sensor; a first semiconductor substrate having a memory; a second semiconductor substrate having a logic circuit; and a second sensor, wherein
the first sensor, the first semiconductor substrate, the second semiconductor substrate, and the second sensor are arranged in this order.
2. The solid-state imaging apparatus according to claim 1 , wherein
an electrode of a first wiring layer formed on a front surface side of the first semiconductor substrate and an electrode of a second wiring layer formed on a front surface side of the second semiconductor substrate are bonded so as to face each other and are electrically connected.
3. The solid-state imaging apparatus according to claim 1 , wherein
the second semiconductor substrate is electrically connected to each of the first sensor and the second sensor.
4. The solid-state imaging apparatus according to claim 1 , wherein
the second semiconductor substrate is connected to each of the first semiconductor substrate and the second sensor by a copper wiring.
5. The solid-state imaging apparatus according to claim 1 , wherein
the second semiconductor substrate is connected to the first sensor by a through via penetrating the first semiconductor substrate.
6. The solid-state imaging apparatus according to claim 1 , wherein
the logic circuit controls data written onto the memory from the first sensor and the second sensor or data read from the memory.
7. The solid-state imaging apparatus according to claim 1 , wherein
the logic circuit controls a timing of writing data onto the memory from the first sensor and the second sensor or a timing of reading data from the memory.
8. The solid-state imaging apparatus according to claim 1 , wherein
the memory includes a dynamic random access memory (DRAM).
9. The solid-state imaging apparatus according to claim 1 , wherein
the memory includes static random access memory (SRAM).
10. The solid-state imaging apparatus according to claim 1 , wherein
the first sensor and the second sensor include a color filter, an on-semiconductor chip lens, and a photoelectric conversion unit.
11. The solid-state imaging apparatus according to claim 10 , wherein
the color filter and the on-semiconductor chip lens are provided on a back surface side of the photoelectric conversion unit.
12. The solid-state imaging apparatus according to claim 1 , further comprising:
a flexible printed substrate; and a cover glass.
13. An electronic equipment, comprising the solid-state imaging apparatus according to claim 1 .
14. A method for manufacturing a solid-state imaging apparatus, the method comprising:
bonding a first electrode formed on one surface of a first semiconductor substrate having a memory and a second electrode formed on one surface of a second semiconductor substrate having a logic circuit such that the first electrode and the second electrode face each other;
after the bonding, stacking a second sensor on another surface not bonded to the second semiconductor substrate; and
after stacking the second sensor, stacking a first sensor on another surface not bonded to the first semiconductor substrate.
15. A method for manufacturing a solid-state imaging apparatus, the method comprising:
stacking a first sensor on one surface of a first semiconductor substrate having a memory;
stacking a second sensor on one surface of a second semiconductor substrate having a logic circuit; and
after stacking the respective first sensor and the second sensor, bonding a first electrode formed on another surface not bonded to the first semiconductor substrate and a second electrode formed on another surface not bonded to the second semiconductor substrate such that the first electrode and the second electrode face each other.