IP Library › Granted Patent US 11,404,107
Granted Patent B2
US 11,404,107 · App. 17/041,037 · Granted Aug 2, 2022

Memory device and electronic device

Inventors: Shunpei Yamazaki (Tokyo, JP); Kiyoshi Kato (Kanagawa, JP); Takahiko Ishizu (Kanagawa, JP); Tatsuya Onuki (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
G11C11/4085H01L27/1052H01L27/124H01L27/1207H01L27/1225H01L27/1255H01L29/24H01L29/7869H01L29/78648
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Quick Facts
Patent No.
US 11,404,107
App. No.
17/041,037
Granted
Aug 2, 2022
Kind
B2
Abstract

A memory device having long data retention time and high reliability is provided. The memory device includes a driver circuit and a plurality of memory cells, the memory cell includes a transistor and a capacitor, and the transistor includes a metal oxide in a channel formation region. The transistor includes a first gate and a second gate, and in a period during which the memory cell retains data, negative potentials are applied to the first gate and the second gate of the transistor.

Claims (49)

1. A memory device comprising:

a driver circuit; and

a plurality of memory cells,

wherein each memory cell comprises a transistor and a capacitor,

wherein one of a source and a drain of the transistor is electrically connected to one electrode of the capacitor,

wherein the transistor comprises a metal oxide in a channel formation region,

wherein the transistor comprises a first gate and a second gate,

wherein the first gate and the second gate have a region where they overlap each other with the channel formation region therebetween,

wherein the driver circuit has a function of driving the first gate,

wherein in a period during which the memory cell retains data, the driver circuit outputs a first potential lower than a potential applied to the source and the drain of the transistor, to the first gate, and

wherein a second potential lower than the potential applied to the source and the drain of the transistor is applied to the second gate.

2. The memory device according to claim 1 ,

wherein the second potential is lower than the first potential.

3. A memory device comprising:

a driver circuit; and

a plurality of memory cells,

wherein each memory cell comprises a transistor and a capacitor,

wherein one of a source and a drain of the transistor is electrically connected to one electrode of the capacitor,

wherein the transistor comprises a metal oxide in a channel formation region,

wherein the transistor comprises a first gate and a second gate,

wherein the first gate and the second gate have a region where they overlap each other with the channel formation region therebetween,

wherein the driver circuit has a function of driving the first gate and the second gate,

wherein in a period during which the memory cell retains data, the driver circuit outputs a first potential lower than a potential applied to the source and the drain of the transistor, to the first gate, and

wherein in the period during which the memory cell retains data, the driver circuit outputs a second potential lower than the potential applied to the source and the drain of the transistor, to the second gate.

4. The memory device according to claim 1 ,

wherein the metal oxide contains at least one or both of In (indium) and Zn (zinc).

5. The memory device according to claim 1 ,

wherein the metal oxide contains Ga (gallium).

6. An electronic device comprising the memory device according to claim 1 .

7. A method for driving a semiconductor device,

wherein the semiconductor device comprises a driver circuit and a memory cell,

wherein the memory cell comprises a transistor and a capacitor,

wherein one of a source and a drain of the transistor is electrically connected to one electrode of the capacitor,

wherein the transistor comprises a first gate and a second gate that overlap each other with a channel formation region therebetween,

wherein the driving method comprises:

a first step of applying a first potential to the first gate and applying a second potential to the other of the source and the drain of the transistor; and

a second step of applying a third potential to the first gate,

wherein the third potential is lower than a potential of the source and the drain of the transistor, and

wherein a fourth potential lower than the potential of the source and the drain of the transistor is applied to the second gate through the first and second steps.

8. The memory device according to claim 2 ,

wherein the metal oxide contains at least one or both of In (indium) and Zn (zinc).

9. The memory device according to claim 2 ,

wherein the metal oxide contains Ga (gallium).

10. An electronic device comprising the memory device according to claim 2 .

11. The memory device according to claim 3 ,

wherein the metal oxide contains at least one or both of In (indium) and Zn (zinc).

12. The memory device according to claim 3 ,

wherein the metal oxide contains Ga (gallium).

13. An electronic device comprising the memory device according to claim 3 .

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 24, 2020
From: YAMAZAKI, SHUNPEI; KATO, KIYOSHI; ISHIZU, TAKAHIKO; ONUKI, TATSUYA
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 053869/0284 →
Priority Claims (2)
JP JP2018-065571 · Mar 29, 2018 · national
JP JP2018-169247 · Sep 10, 2018 · national
Continuity (1)
Related Publication 20210027828A1 · Jan 28, 2021
Cited By (1)
US 12,260,898