Power control arbitration

1. An apparatus of a local power control arbiter to interface with a global power control unit of a processing platform having a plurality of processing entities, the apparatus including the local power control arbiter to control a local processing unit of the processing platform, the apparatus comprising:

an interface to receive, from the global power control unit, a local performance limit allocated to the local processing unit depending on a global power control evaluation;

a local to global mailbox having one or more hardware registers to enable the local power control arbiter to send commands to the global power control unit, wherein the local to global mailbox comprises:

a first register field to identify which one of the plurality of processing entities of the processing platform currently has control of the local to global mailbox; and

a second register field to disable any write attempt to the local to global mailbox from a processing entity other than the currently controlling processing entity; and

processing circuitry to:

determine any change to one or more processing conditions prevailing in the local processing unit on a timescale shorter than a duration for which the local performance limit is applied to the local processing unit by the global power control unit; and

configure a performance level for the local processing unit depending on both the local performance limit and the determined change to the prevailing processing conditions on the local processing unit.

2. The apparatus of claim 1 , wherein the local performance limit comprises at least one of: a frequency upper limit, a voltage upper limit, a power upper limit, and a current upper limit.

3. The apparatus of claim 1 , wherein the duration for which the local performance limit is applied to the local processing unit by the global power control unit is greater than 100 microseconds whereas a timescale within which any change to the processing conditions is determined is in a range of between 10 micro seconds and 100 microseconds.

4. The apparatus of claim 1 , wherein the determined change in processing conditions comprises at least one of: a change in a number of threads executing on the processing unit, a change in a processing workload, and a change in utilization of the processing unit.

5. The apparatus of claim 1 , wherein the processing circuitry is to receive, from the local processing unit, a request to change a performance level of the local processing unit and to relay the performance level change request to the global power control unit for a subsequent global power evaluation to update the local performance limit.

6. The apparatus of claim 1 , wherein the local power control arbiter is to manage at least one of:

a threshold power for at least one processing entity of the local processing unit; a threshold current for at least one processing entity of the local processing unit;

one or more turbo ratio limits for at least one processing entity of the local processing unit; and

a scalability of a processing workload executing on at least one processing entity of the local processing unit.

7. The apparatus of claim 1 , comprising a work point arbiter to arbitrate between the local performance limit determined by the global power control unit and a local power constraint requested by the local processing unit.

8. The apparatus of claim 7 , wherein the work point arbiter is to select between a plurality of different local performance levels for one or more processing entities of the local processing unit within the constraint of the local performance limit.

9. The apparatus of claim 8 , wherein the local performance levels are selected based on predetermined values stored in a set of registers.

10. The apparatus of claim 1 , comprising a microprocessor, a non-volatile memory, and an input/output interface.

11. The apparatus of claim 1 , wherein the local processing unit comprises one of: a processor core, a graphics processing unit and an image processing unit.

12. The apparatus of claim 1 , comprising a global to local mailbox having one or more hardware registers to send commands from the global power control unit to the local power control arbiter.

13. The apparatus of claim 12 , wherein the global to local mailbox has a register field to allow selection of one of a plurality of processing units to receive commands from the global power control unit.

14. The apparatus of claim 1 , wherein the processing circuitry is to load configuration data for from a basic input output system, BIOS, of an operating system of the processing platform during a reset operation.

15. A processing platform comprising:

a plurality of processing entities;

a global power control unit to control a performance level of the plurality of processing entities; and

at least one local power control arbiter that includes:

an interface to receive, from the global power control unit, a local performance limit allocated to the local processing unit depending on a global power control evaluation;

a local to global mailbox having one or more hardware registers to enable the local power control arbiter to send commands to the global power control unit, wherein the local to global mailbox comprises:

a first register field to identify which one of the plurality of processing entities of the processing platform currently has control of the local to global mailbox; and

a second register field to disable any write attempt to the local to global mailbox from a processing entity other than the currently controlling processing entity; and

processing circuitry to:

determine any change to one or more processing conditions prevailing in the local processing unit on a timescale shorter than a duration for which the local performance limit is applied to the local processing unit by the global power control unit; and

configure a performance level for the local processing unit depending on both the local performance limit and the determined change to the prevailing processing conditions on the local processing unit, wherein at least one subset of the plurality of processing entities is controlled by a respective local power control arbiter.

16. The processing platform as claimed in claim 15 , comprising a plurality of local power control arbiters to control a respective plurality of processing units of the processing platform, each processing unit having at least one processor core.

17. The processing platform as claimed in claim 15 , wherein the processing platform is included in an integrated circuit.

18. Machine readable instructions provided on a non-transitory machine-readable medium that, when executed by one or more processors of a local power control arbiter are to:

receive, from a global power control unit of a processing platform, a local performance limit allocated to a local processing unit of the processing platform depending on a global power control evaluation;

provide a local to global mailbox having one or more registers to enable the local power control arbiter to send commands to the global power control unit, wherein the local to global mailbox comprises:

a first register field to identify which one of the plurality of processing entities of the processing platform currently has control of the local to global mailbox; and

a second register field to disable any write attempt to the local to global mailbox from a processing entity other than the currently controlling processing entity;

determine any change to one or more processing conditions prevailing in the local processing unit on a timescale shorter than a duration for which the local performance limit is applied to the local processing unit by the global power control unit; and

configure a performance level for the local processing unit depending on both the local performance limit and the determined change to the prevailing processing conditions on the local processing unit.

19. Machine readable instructions as claimed in claim 18 , wherein the local performance limit comprises a frequency upper limit for the processing unit and wherein the frequency upper limit applies to one or more processor cores of the processing unit.

20. A method of controlling a performance level of a local processing unit of a processing platform comprising a global power control unit, the method comprising:

receiving from the global power control unit, a local performance limit allocated to the local processing unit of the processing platform depending on a global power control evaluation;

providing a local to global mailbox having one or more registers to enable a local power control arbiter to send commands to the global power control unit, wherein the local to global mailbox comprises:

a first register field to identify which one of the plurality of processing entities of the processing platform currently has control of the local to global mailbox; and

a second register field to disable any write attempt to the local to global mailbox from a processing entity other than the currently controlling processing entity;

determining any change to one or more processing conditions prevailing in the local processing unit on a timescale shorter than a duration for which the local performance limit is applied to the local processing unit by the global power control unit; and

configuring a performance level for the local processing unit depending on both the local performance limit and the determined change to the prevailing processing conditions on the local processing unit.

21. The method of claim 20 , comprising receiving from the local processing unit a request for a change to a performance level of the processing unit and relaying the request to the global power control unit to update the local performance limit.