Secure collaboration between processors and processing accelerators in enclaves

1. A system for providing a secure collaboration between one or more PCIe accelerators and an enclave defined within memory of a host computing device, the system comprising:

a PCIe accelerator apparatus including:

the one or more PCIe accelerators;

a microcontroller configured to provide a cryptographic hardware identity to the PCIe accelerator apparatus, wherein the PCIe accelerator apparatus is configured to use the cryptographic hardware identity to negotiate a cryptographic session between the PCIe accelerator apparatus and the enclave; and

a cryptographic engine separate from the one or more PCIe accelerators and arranged in a PCIe path of the one or more PCIe accelerators to provide encryption and decryption operations between the one or more PCIe accelerators and the enclave during the cryptographic session.

2. The system of claim 1 , further comprising a circuit board on which each of the one or more PCIe accelerators and the microcontroller are arranged.

3. The system of claim 1 , wherein each of the one or more PCIe accelerators is one of a tensor processing unit or a graphical processing unit.

4. The system of claim 1 , wherein the PCIe accelerator apparatus further comprises an application processor configured to communicate with the enclave.

5. The system of claim 4 , wherein the application processor is incorporated into the microcontroller.

6. The system of claim 4 , wherein the application processor further includes a dedicated function for communicating with an operating system of a computing device on which the enclave resides.

7. The system of claim 6 , wherein the dedicated function is configured to enable a communication path between the application processor and the enclave via the computing device.

8. The system of claim 1 , wherein the cryptographic engine is configured to decrypt information from the enclave that is entering the PCIe accelerator apparatus during the cryptographic session.

9. The system of claim 1 , wherein the cryptographic engine is configured to encrypt information from the PCIe accelerator apparatus that is entering the enclave during the cryptographic session.

10. The system of claim 1 , wherein the cryptographic engine is a line-rate cryptographic engine.

11. The system of claim 1 , wherein the PCIe accelerator apparatus further comprises an application processor configured to manage keys used by the cryptographic engine.

12. The system of claim 1 , wherein the cryptographic engine is a separate component from the one or more PCIe accelerators in the PCIe accelerator apparatus.

13. The system of claim 1 , wherein the cryptographic engine is arranged between the one or more PCIe accelerators and the enclave.

14. A method for providing a secure collaboration between one or more PCIe accelerators of a PCIe accelerator apparatus and an enclave defined within memory of a host computing device, the method comprising:

negotiating, by the PCIe accelerator apparatus, a cryptographic session with the enclave using a cryptographic hardware identity provided by a microcontroller of the PCIe accelerator apparatus; and

during the cryptographic session:

retrieving, by the PCIe accelerator apparatus, encrypted one or both of code or data from the enclave;

decrypting, by a cryptographic engine of the PCIe accelerator apparatus, the encrypted one or both of code or data, the cryptographic engine being separate from the one or more PCIe accelerators and arranged in a PCIe path of the one or more PCIe accelerators;

retrieving, by the one or more PCIe accelerators, the unencrypted one or both of code or data;

processing, by the one or more PCIe accelerators, the unencrypted one or both of code or data to generate results;

encrypting, by the cryptographic engine, the results; and

sending, by the PCIe accelerator apparatus, the encrypted results back to the enclave.

15. The method of claim 14 , wherein the cryptographic session is negotiated through host OS-mediated communication.

16. The method of claim 14 , wherein the encrypted one or both of code or data are retrieved using direct memory access.

17. The method of claim 14 , wherein the encrypted results are sent using direct memory access.

18. A non-transitory computer-readable medium storing instructions executable by one or more processors for providing a secure collaboration between one or more PCIe accelerators of a PCIe accelerator apparatus and an enclave defined within memory of a host computing device, the instructions comprising:

negotiating a cryptographic session with the enclave using a cryptographic hardware identity provided by a microcontroller of the PCIe accelerator apparatus; and

during the cryptographic session:

retrieving encrypted one or both of code or data from the enclave;

decrypting the encrypted one or both of code or data using a cryptographic engine, the cryptographic engine being separate from the one or more PCIe accelerators and arranged in a PCIe path of the one or more PCIe accelerators;

retrieving the unencrypted one or both of code or data;

processing the unencrypted one or both of code or data to generate results;

encrypting the results using the cryptographic engine; and

sending the encrypted results back to the enclave.