IP Library Granted Patent US 11,935,899
Granted Patent B2
US 11,935,899 · App. 17/047,740 · Granted Mar 19, 2024

Semiconductor device

Inventors: Takahiko Ishizu (Kanagawa, JP); Seiichi Yoneda (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L27/124H01L27/1259H01L29/24H03K19/00315H03K19/017H03K19/0941H03K19/20
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Quick Facts
Patent No.
US 11,935,899
App. No.
17/047,740
Granted
Mar 19, 2024
Kind
B2
Abstract

A semiconductor device capable of stable operation with low power consumption is provided. A logic circuit having a circuit configuration using a transistor including an oxide semiconductor in a channel formation region is included. The logic circuit is a two-input/two-output two-wire logic circuit. Transistors included in the logic circuit each include a gate and a back gate. An input terminal is electrically connected to one of a gate and a back gate of a transistor electrically connected to a wiring for supplying a high power supply potential. An output terminal is connected to the other of the gate and the back gate of the transistor electrically connected to the wiring for supplying a high power supply potential. An output terminal is electrically connected to one of a source and a drain of a transistor electrically connected to a wiring for supplying a low power supply potential. A gate or a back gate of the transistor electrically connected to the wiring for supplying a low power supply potential is electrically connected to an input terminal.

Claims (15)

1. A semiconductor device comprising:

a first input terminal and a second input terminal;

a first output terminal and a second output terminal;

a first wiring and a second wiring; and

first to fourth transistors,

wherein one of a source and a drain of the first transistor is electrically connected to the first wiring, one of a gate and a back gate is electrically connected to the first input terminal, and the other of the source and the drain and the other of the gate and the back gate are electrically connected to the second output terminal,

wherein one of a source and a drain of the second transistor is electrically connected to the first wiring, one of a gate and a back gate is electrically connected to the second input terminal, and the other of the source and the drain and the other of the gate and the back gate are electrically connected to the first output terminal,

wherein a gate and a back gate of the third transistor are electrically connected to the first input terminal, one of a source and a drain is electrically connected to the first output terminal, and the other of the source and the drain is electrically connected to the second wiring, and

wherein a gate and a back gate of the fourth transistor are electrically connected to the second input terminal, one of a source and a drain is electrically connected to the second output terminal, and the other of the source and the drain is electrically connected to the second wiring.

2. The semiconductor device according to claim 1 ,

wherein the first to fourth transistors are each a transistor comprising a metal oxide in a channel formation region.

3. The semiconductor device according to claim 2 ,

wherein the metal oxide comprises at least In (indium) or Zn (zinc).

4. The semiconductor device according to claim 3 ,

wherein the metal oxide comprises Ga (gallium).

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 15, 2020
From: ISHIZU, TAKAHIKO; YONEDA, SEIICHI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 054060/0526 →
Priority Claims (2)
JP 2018-081075 · Apr 20, 2018 · national
JP 2018-085916 · Apr 27, 2018 · national
Continuity (1)
Related Publication 20210167095A1 · Jun 3, 2021