Display panel
View Patent ↗The present application provides a display panel. The display panel includes multiple sub-pixels, multiple data lines, multiple scan lines, and multiple gate fan-out lines. Each two columns of the sub-pixels constitute a sub-pixel group, two data lines are arranged between the two columns of the sub-pixels in the sub-pixel group, and any two adjacent gate fan-out lines are spaced by at least one sub-pixel group. A width of the gate fan-out line is not less than a sum of widths of the two data lines in the sub-pixel group.
1. A display panel, comprising a display region and a non-display region arranged at one side of the display region, wherein the display region comprises:
a plurality of sub-pixels arranged in rows and columns;
a plurality of data lines arranged in a one-to-one correspondence with the columns of the sub-pixels;
a plurality of scan lines arranged in a one-to-one correspondence with the rows of the sub-pixels; and
a plurality of gate fan-out lines connected to the scan lines in a one-to-one correspondence;
wherein the data lines and the gate fan-out lines extend in a column direction to the non-display region, each two columns of the sub-pixels constitute a sub-pixel group, two data lines are arranged between the two columns of the sub-pixels in the sub-pixel group, and each two adjacent gate fan-out lines are spaced by at least one of the sub-pixel groups; and
wherein a gap is defined between the two data lines in the sub-pixel group, and a width of the gate fan-out line is equal to a sum of widths of the two data lines in the sub-pixel group and a width of the gap.
2. The display panel according to claim 1 , wherein the gate fan-out lines and the data lines are arranged in a same layer, and the gate fan-out lines are arranged in a different layer from the scan lines.
3. The display panel according to claim 1 , wherein a gate insulating layer is arranged between the gate fan-out lines and the scan lines, via holes are defined in the gate insulating layer, and the gate fan-out lines are electrically connected to the corresponding scan lines through the via holes.
4. The display panel according to claim 1 , wherein the display panel further comprises a light shielding layer; and
the light shielding layer is arranged corresponding to the data lines, the scan lines, and the gate fan-out lines.
5. The display panel according to claim 4 , wherein the light shielding layer comprises a plurality of first light shielding patterns and a plurality of second light shielding patterns; and
orthographic projections of the first light shielding patterns projected on a layer where the gate fan-out lines are located completely cover the gate fan-out lines, and orthographic projections of the second light-shielding patterns projected on a layer where the data lines are located completely cover the two data lines in the sub-pixel group.
6. The display panel according to claim 5 , wherein a length of the first light shielding pattern in a row direction is equal to a length of the second light shielding pattern in the row direction.
7. The display panel according to claim 1 , wherein the non-display region comprises a gate driving circuit and a source driving circuit; and
the gate driving circuit is electrically connected to the gate fan-out lines, and the source driving circuit is electrically connected to the data lines.
8. The display panel according to claim 7 , wherein the gate driving circuit comprises multi-stage gate driving units; and
the multi-stage gate driving units are electrically connected to the gate fan-out lines in a one-to-one correspondence.
9. The display panel according to claim 8 , wherein the source driving circuit is arranged at one side of the gate driving circuit away from the display region, and the multi-stage gate driving units are arranged in parallel and spaced apart from each other; and
the data lines extend to the source driving circuit through gaps between the multi-stage gate driving units, and are electrically connected to the source driving circuit.
10. A display panel, comprising a display region and a non-display region arranged at one side of the display region, wherein the display region comprises:
a plurality of sub-pixels arranged in rows and columns;
a plurality of data lines arranged in a one-to-one correspondence with the columns of the sub-pixels;
a plurality of scan lines arranged in a one-to-one correspondence with the rows of the sub-pixels; and
a plurality of gate fan-out lines connected to the scan lines in a one-to-one correspondence;
wherein the data lines and the gate fan-out lines extend in a column direction to the non-display region, each two columns of the sub-pixels constitute a sub-pixel group, two data lines are arranged between the two columns of the sub-pixels in the sub-pixel group, and each two adjacent gate fan-out lines are spaced by at least one of the sub-pixel groups;
wherein a width of the gate fan-out line is greater than or equal to a sum of widths of the two data lines in the sub-pixel group.
11. The display panel according to claim 10 , wherein the gate fan-out lines and the data lines are arranged in a same layer, and the gate fan-out lines and the scan lines are arranged in different layers.
12. The display panel according to claim 10 , wherein a gate insulating layer is arranged between the gate fan-out lines and the scan lines, via holes are defined in the gate insulating layer, and the gate fan-out lines are electrically connected to the corresponding scan lines through the via holes.
13. The display panel according to claim 10 , wherein the display panel further comprises a light shielding layer; and
the light shielding layer is arranged corresponding to the data lines, the scan lines, and the gate fan-out lines.
14. The display panel according to claim 13 , wherein the light shielding layer comprises a plurality of first light shielding patterns and a plurality of second light shielding patterns; and
orthographic projections of the first light shielding patterns projected on a layer where the gate fan-out lines are located completely cover the gate fan-out lines, and orthographic projections of the second light shielding patterns projected on a layer where the data lines are located completely cover the two data lines in the sub-pixel group.
15. The display panel according to claim 14 , wherein a length of the first light shielding pattern in a row direction is the same as a length of the second light shielding pattern in the row direction.
16. The display panel according to claim 10 , wherein the non-display region comprises a gate driving circuit and a source driving circuit; and
the gate driving circuit is electrically connected to the gate fan-out lines, and the source driving circuit is electrically connected to the data lines.
17. The display panel according to claim 16 , wherein the gate driving circuit comprises multi-stage gate driving units; and
the multi-stage gate driving units are electrically connected to the gate fan-out lines in a one-to-one correspondence.
18. The display panel according to claim 17 , wherein the source driving circuit is arranged at one side of the gate driving circuit away from the display region, and the multi-stage gate driving units are arranged in parallel and spaced apart from each other; and
the data lines extend to the source driving circuit through gaps between the multi-stage gate driving units, and are electrically connected to the source driving circuit.