IP Library Granted Patent US 12,271,319
Granted Patent B2
US 12,271,319 · App. 17/054,762 · Granted Apr 8, 2025

Data stored or free space based FIFO buffer

Inventors: Yanjie Pan (Shanghai, CN); Yong Jiang (Shanghai, CN); Yuanyuan Li (Shanghai, CN); Yong Zhang (Hillsboro, OR)
Assignee: Intel Corporation
G06F12/123G06F5/06G06F5/12G06F12/0893G06F2212/1044
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Quick Facts
Patent No.
US 12,271,319
App. No.
17/054,762
Granted
Apr 8, 2025
Kind
B2
Abstract

Systems, methods, and computer-readable media are provided for variable precision first in, first out (FIFO) buffers (VPFB) that dynamically changes the amount of data to be stored in the VPFB based on a current amount of data stored in the VPFB and/or based on a current amount of available memory space of the VPFB. The currently unavailable memory space (or the current available memory space) is used to select the size of a next data block to be stored in the VPFB. Other embodiments are disclosed and/or claimed.

Claims (26)

1. Communication circuitry comprising:

radiofrequency (RF) circuitry coupled to an antenna array; and

baseband circuitry communicatively coupled with the RF circuitry, wherein the baseband circuitry is operable to:

obtain a quantized data sample;

determine an occupancy of a first in first out (FIFO) buffer;

select a first quantization precision of the quantized data sample to be stored in the FIFO buffer based on a first occupancy of the FIFO buffer;

select a second quantization precision of the quantized data sample based on the occupancy of the FIFO buffer being greater than the first occupancy;

if the first quantization precision is selected, then store the quantized data sample in the FIFO buffer; and

if the second quantization precision is selected, then:

store a selected number of bits of the quantized data sample in the FIFO buffer; and

discard a remaining number of bits of the quantized data sample that are not the selected number of bits.

2. The communication circuitry of claim 1 , wherein the baseband circuitry is operable to:

determine whether to select the first or second quantization precision in response to receipt of the quantized data sample from the RF circuitry.

3. The communication circuitry of claim 1 , wherein the baseband circuitry is operable to:

select the first quantization precision when a current amount of data stored in the FIFO buffer is less than a first threshold value related to the occupancy of the FIFO buffer;

select the second quantization precision when the current amount of data stored in the FIFO buffer is greater than or equal to the first threshold value and less than a second threshold value related to the occupancy of the FIFO buffer, wherein the second quantization precision is half of the first quantization precision;

select a third quantization precision when the current amount of data stored in the FIFO buffer is greater than or equal to the second threshold value and less than a size threshold of the FIFO buffer, wherein the third quantization precision is half of the second quantization precision; and

discard the quantized data sample when the current amount of data stored in the FIFO buffer is in excess of the size threshold of the FIFO buffer.

4. The communication circuitry of claim 1 , wherein the baseband circuitry is operable to:

select the first quantization precision when an amount of currently free space in the FIFO buffer is greater than a first threshold value related to the occupancy of the FIFO buffer;

select the second quantization precision when the amount of currently free space in the FIFO buffer is less than or equal to the first threshold value and greater than a second threshold value related to the occupancy of the FIFO buffer, wherein the second quantization precision is half of the first quantization precision;

select a third quantization precision when the amount of currently free space in the FIFO buffer is less than or equal to the second threshold value and greater than a free space limit of the FIFO buffer, wherein the third quantization precision is half of the second quantization precision; and

discard the quantized data sample when the amount of currently free space is less than or equal to the free space limit of the FIFO buffer.

5. The communication circuitry of claim 3 , wherein the baseband circuitry is operable to generate the quantized data sample, and to provide the quantized data sample to the RF circuitry on a transmit signal path, and wherein the quantized data sample represents a sample of a digital baseband signal, and the number of bits represents a quantization precision of the digital baseband signal.

6. The communication circuitry of claim 3 , wherein the baseband circuitry is operable to receive the quantized data sample from the RF circuitry, and wherein the quantized data sample represents a sample of an analog signal, and the number of bits represents a quantization precision of the analog signal.

7. The communication circuitry of claim 3 , wherein the FIFO buffer is implemented in a scratchpad memory device of the baseband circuitry.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2025
From: INTEL CORPORATION
To: SK HYNIX NAND PRODUCT SOLUTIONS CORP. (DBA SOLIDIGM)
Reel/Frame 072549/0289 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 3, 2025
From: PAN, YANJIE; JIANG, YONG; LI, YUANYUAN; ZHANG, YONG
To: INTEL CORPORATION
Reel/Frame 069730/0744 →
Continuity (1)
Related Publication 20210248087A1 · Aug 12, 2021
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