Techniques of user equipment receiver power switching
Methods and devices including a processing circuit for a User Equipment, UE, wherein the UE includes a radio frequency, RF, receiver, wherein the processing circuit is configured to set a power switching pattern of the RF receiver for UE power saving in Discontinuous Reception, DRX, Radio Resource Control, RRC, IDLE mode based on a paging occasion, PO, and a signal block associated with the PO.
1. A processing circuit for a User Equipment (UE), wherein the UE comprises a radio frequency (RF) receiver, wherein the processing circuit is configured to:
set a power switching pattern of the RF receiver for UE power saving in Discontinuous Reception (DRX) Radio Resource Control (RRC) IDLE mode based on a paging occasion (PO) and a synchronization signal block associated with the PO, wherein the power switching pattern comprises a switching off of the RF receiver within a reception time period that is defined for receiving the PO and the synchronization signal block.
2. The processing circuit of claim 1 , configured to:
set the power switching pattern based on a time gap between the PO and the synchronization signal block associated with the PO.
3. The processing circuit of claim 2 ,
wherein the switching off is configured to occur during at least part of the time gap between the PO and the synchronization signal block associated with the PO.
4. The processing circuit of claim 1 , configured to:
set the power switching pattern of the RF receiver based on channel condition measurements.
5. The processing circuit of claim 1 , configured to:
set the power switching pattern based on a central carrier of the PO and a central carrier of the synchronization signal block associated with the PO.
6. The processing circuit of claim 1 , configured to:
set the power switching pattern based on a bandwidth gap between an RF bandwidth of the PO and an RF bandwidth of the synchronization signal block associated with the PO.
7. The processing circuit of claim 6 ,
wherein the power switching pattern comprises a switching off within at least part of the bandwidth gap between the PO and the synchronization signal block associated with the PO.
8. The processing circuit of claim 1 ,
wherein the power switching pattern comprises an OFF to ON transition, skipping at least one preceding reference symbols within the synchronization signal block associated with the PO.
9. The processing circuit of claim 8 , configured to:
activate preceding Primary Synchronization Signal (PSS) symbol skipping if a received power of a colliding PSS from a neighbor cell is higher than a pre-defined threshold while a timing offset error is lower than a second pre-defined threshold.
10. The processing circuit of claim 9 , wherein the OFF to ON transition of the power switching pattern is finished before a Physical Broadcast Channel Demodulation Reference Signal (PBCH DMRS) symbol within the synchronization signal block associated with the PO preserving the PBCH DMRS symbol.
11. The processing circuit of claim 8 , configured to:
set the power switching pattern based on a second time gap between the PO and a second synchronization signal block associated with the PO, the second synchronization signal block preceding the synchronization signal block associated with the PO, if a time gap between the PO and the synchronization signal block associated with the PO is shorter than a transition time interval of the RF receiver.
12. The processing circuit of claim 11 ,
wherein a sum of an OFF to ON transition and an ON to OFF transition of the power switching pattern corresponds to the transition time interval of the RF receiver.
13. The processing circuit of claim 1 ,
wherein the power switching pattern comprises an ON to OFF transition skipping at least one succeeding reference symbol within the synchronization signal block associated with the PO.
14. The processing circuit of claim 13 , configured to:
activate succeeding PBCH DMRS symbol skipping if a received power of a colliding PSS from a neighbor cell is lower than a pre-defined threshold while a timing offset error is higher than a second pre-defined threshold.
15. The processing circuit of claim 13 ,
wherein the ON to OFF transition of the power switching pattern starts after a Primary Synchronization Signal (PSS) symbol within the synchronization signal block associated with the PO preserving the PSS symbol.
16. The processing circuit of claim 1 ,
wherein the power switching pattern comprises an OFF to ON transition preceding a first reference symbol within the synchronization signal block associated with the PO and an ON to OFF transition succeeding a last reference symbol within the synchronization signal block associated with the PO.
17. The processing circuit of claim 1 , configured to:
set the power switching pattern of the RF receiver for a next DRX cycle based on channel parameter estimations on reference signals received from one or more preceding DRX cycles.
18. The processing circuit of claim 1 , configured to:
switch off reception of the synchronization signal block associated with the PO in a subset of DRX cycles; and
switch on reception of the synchronization signal block associated with the PO in the remaining subset of DRX cycles.
19. A method for power switching a radio frequency (RF), receiver of a User Equipment (UE) wherein the method comprises:
setting a power switching pattern of the RF receiver for UE power saving in Discontinuous Reception (DRX) Radio Resource Control (RRC) IDLE mode based on a paging occasion (PO) and a synchronization signal block associated with the PO, wherein the power switching pattern comprises a switching off of the RF receiver within a reception time period that is defined for receiving the PO and the synchronization signal block; and
switching a power mode of the RF receiver based on the power switching pattern.
20. The method of claim 19 , comprising:
setting the power switching pattern based on a time gap between the PO and the synchronization signal block associated with the PO.