D-type flip-flop circuit
View Patent ↗A D-type flip-flop circuit 1 has a structure in which a pMOS transistor p 8 and an nMOS transistor n 8 are added to a general D-type flip-flop circuit comprising pMOS transistors p 1 to p 7 , p 11 to p 15 and nMOS transistors n 1 to n 7 , n 11 to n 15.
1. A D-type flip-flop circuit, comprising:
a master latch, a transmission gate and a slave latch,
wherein, the master latch comprises a first inverter and a first tri-state inverter,
the first inverter comprises a first pMOS transistor and a first nMOS transistor,
one of a source and a drain of the first pMOS transistor is connected to a power supply potential,
one of a source and a drain of the first nMOS transistor is connected to the other of the source and the drain of the first pMOS transistor, the other of the source and the drain of the first nMOS transistor is grounded, and a gate of the first nMOS transistor is connected to a gate of the first pMOS transistor,
the first tri-state inverter comprises a second pMOS transistor, a third pMOS transistor, a second nMOS transistor, and a third nMOS transistor,
one of a source and a drain of the second pMOS transistor is connected to the power supply potential,
one of a source and a drain of the third pMOS transistor is directly or indirectly connected to the other of the source and drain of the second pMOS transistor, and the other of the source and the drain of the third pMOS transistor is directly or indirectly connected to a first node, and an inverted clock signal is inputted to a gate of the third pMOS transistor,
the first node is connected to the gate of the first pMOS transistor and the gate of the first nMOS transistor, and the first node, the gate of the first pMOS transistor and the gate of the first nMOS transistor together constitute an input part of the master latch,
one of a source and a drain of the second nMOS transistor is directly or indirectly connected to the first node, and a clock signal is inputted to a gate of the second nMOS transistor,
one of a source and a drain of the third nMOS transistor is directly or indirectly connected to the other of the source and the drain of the second nMOS transistor, and the other of the source and the drain of the third nMOS transistor is grounded,
a gate of the second pMOS transistor and a gate of the third nMOS transistor are connected to each other to constitute an output part of the master latch, and are connected to the other of the source and the drain of the first pMOS transistor and to the one of the source and the drain of the first nMOS transistor,
the transmission gate comprises a fourth pMOS transistor and a fourth nMOS transistor,
one of a source and a drain of the fourth pMOS transistor and one of a source and a drain of the fourth nMOS transistor are connected to each other to constitute an input part of the transmission gate, and are connected to the output part of the master latch,
the other of the source and the drain of the fourth pMOS transistor and the other of the source and the drain of the fourth nMOS transistor are connected to each other to constitute an output part of the transmission gate,
the slave latch comprises a second inverter and a second tri-state inverter,
the second inverter comprises a fifth pMOS transistor and a fifth nMOS transistor,
one of a source and a drain of the fifth pMOS transistor is connected to the power supply potential,
one of a source and a drain of the fifth nMOS transistor is connected to the other of the source and the drain of the fifth pMOS transistor, the other of the source and drain of the fifth nMOS transistor is grounded, and a gate of the fifth nMOS transistor is connected to a gate of the fifth pMOS transistor,
the second tri-state inverter comprises a sixth pMOS transistor, a seventh pMOS transistor, a sixth nMOS transistor, and a seventh nMOS transistor,
one of a source and a drain of the sixth pMOS transistor is connected to the power supply potential,
one of a source and a drain of the seventh pMOS transistor is directly or indirectly connected to the other of the source and the drain of the sixth pMOS transistor, and the other of the source and the drain of the seventh pMOS transistor is directly or indirectly connected to a second node, and the clock signal is inputted to a gate of the seventh pMOS transistor,
the second node is connected to the gate of the fifth pMOS transistor and the gate of the fifth nMOS transistor, and the second node, the gate of the fifth pMOS transistor and the gate of the fifth nMOS transistor together constitute an input part of the slave latch,
one of a source and a drain of the sixth nMOS transistor is directly or indirectly connected to the second node, and the inverted clock signal is inputted to a gate of the sixth nMOS transistor,
one of a source and a drain of the seventh nMOS transistor is directly or indirectly connected to the other of the source and the drain of the sixth nMOS transistor, and the other of the source and the drain of the seventh nMOS transistor is grounded,
a gate of the sixth pMOS transistor and a gate of the seventh nMOS transistor are connected to each other to constitute an output part of the slave latch, and are connected to the other of the source and the drain of the fifth pMOS transistor, the one of the source and the drain of the fifth nMOS transistor, and the output part of the transmission gate,
in the D-type flip-flop circuit,
the first tri-state inverter further comprises an eighth pMOS transistor and an eighth nMOS transistor,
one and the other of a source and a drain of the eighth pMOS transistor are respectively connected to the other of the source and the drain of the second pMOS transistor and the one of the source and the drain of the third pMOS transistor, or respectively connected to the other of the source and the drain of the third pMOS transistor and the first node,
one and the other of a source and a drain of the eighth nMOS transistor are respectively connected to the other of the source and the drain of the second nMOS transistor and the one of the source and the drain of the third nMOS transistor, or respectively connected to the first node and the one of the source and the drain of the second nMOS transistor,
a gate of the eighth pMOS transistor and a gate of the eighth nMOS transistor are connected to each other, and are connected to a connection between the other of the source and the drain of the sixth pMOS transistor and the other of the source and the drain of the seventh pMOS transistor and a connection between the other of the source and the drain of the sixth nMOS transistor and the one of the source and the drain of the seventh nMOS transistor.
2. The D-type flip-flop circuit according to claim 1 , wherein,
the one and the other of the source and the drain of the eighth pMOS transistor are respectively connected to the other of the source and the drain of the second pMOS transistor and the one of the source and the drain of the third pMOS transistor,
the one and the other of the source and the drain of the eighth nMOS transistor are respectively connected to the other of the source and the drain of the second nMOS transistor and the one of the source and the drain of the third nMOS transistor.
3. The D-type flip-flop circuit according to claim 1 , wherein,
the one and the other of the source and the drain of the eighth pMOS transistor are respectively connected to the other of the source and the drain of the third nMOS transistor and the first node,
the one and the other of the source and the drain of the eighth nMOS transistor are respectively connected to the first node and the one of the source and the drain of the second nMOS transistor.
4. The D-type flip-flop circuit according to claim 1 , wherein,
the slave latch further comprises a third inverter,
the third inverter comprises a ninth pMOS transistor and a ninth nMOS transistor,
one of a source and a drain of the ninth pMOS transistor is connected to the power supply potential,
one of a source and a drain of the ninth nMOS transistor is connected to the other of the source and the drain of the ninth pMOS transistor, the other of the source and the drain of the ninth nMOS transistor is grounded, and a gate of the ninth nMOS transistor is connected to a gate of the ninth pMOS transistor,
the gate of the ninth pMOS transistor and the gate of the ninth nMOS transistor are inputted with an inverted signal of an output signal from the output part of the slave latch,
the second tri-state inverter further comprises a tenth pMOS transistor and a tenth nMOS transistor,
one and the other of a source and a drain of the tenth pMOS transistor are respectively connected to the other of the source and the drain of the sixth pMOS transistor and the one of the source and the drain of the seventh pMOS transistor, or respectively connected to the other of the source and the drain of the seventh pMOS transistor and the second node,
one and the other of a source and a drain of the tenth nMOS transistor are respectively connected to the other of the source and the drain of the sixth nMOS transistor and the one of the source and the drain of the seventh nMOS transistor, or respectively connected to the second node and the one of the source and the drain of the sixth nMOS transistor,
a gate of the tenth pMOS transistor and a gate of the tenth nMOS transistor are connected to each other and are connected to the other of the source and the drain of the ninth pMOS transistor and the one of the source and the drain of the ninth nMOS transistor.
5. The D-type flip-flop circuit according to claim 4 , wherein,
the one and the other of the source and the drain of the tenth pMOS transistor are respectively connected to the other of the source and the drain of the sixth pMOS transistor and the one of the source and the drain of the seventh pMOS transistor,
the one and the other of the source and drain of the tenth nMOS transistor are respectively connected to the other of the source and the drain of the sixth nMOS transistor and the one of the source and the drain of the seventh nMOS transistor.
6. The D-type flip-flop circuit according to claim 4 , wherein,
the one and the other of the source and the drain of the tenth pMOS transistor are respectively connected to the other of the source and the drain of the seventh pMOS transistor and the second node,
the one and the other of the source and the drain of the tenth nMOS transistor are respectively connected to the second node and the one of the source and the drain of the sixth nMOS transistor.