IP Library › Granted Patent US 11,927,619
Granted Patent B2
US 11,927,619 · App. 17/059,857 · Granted Mar 12, 2024

Power semi-conductor module, mask, measurement method, computer software, and recording medium

Inventor: Nicolas Degrenne (Rennes, FR)
Assignee: MITSUBISHI ELECTRIC CORPORATION
G01R31/2644G01R31/2642H01L23/34H01L29/7397H01L29/7803H01L29/7813G01R31/275
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Quick Facts
Patent No.
US 11,927,619
App. No.
17/059,857
Granted
Mar 12, 2024
Kind
B2
Abstract

Power semi-conductor module ( 1 ) comprising: —at least one IGBT with a Gate G forming a first electrode ( 11 ) and an Emitter E forming a second electrode ( 12 ), or —at least one MOSFET with a Gate G forming a first electrode ( 11 ) and a Source S forming a second electrode ( 12 ). The first electrode ( 11 ) includes a polysilicon material made in one piece. The one-piece is made partly of a monitoring portion ( 13 ). The monitoring portion ( 13 ) is in electrical contact with the second electrode ( 12 ) such that a leakage current flows between the first electrode ( 11 ) and the second electrode ( 12 ) in an operational state of the module ( 1 ). The monitoring portion ( 13 ) has a location, a form, a size and a material composition selected together such that to have a variable resistance in function of its temperature during the operational state of the module ( 1 ).

Claims (37)

1. Power semi-conductor module comprising:

at least one Insulated Gate Bipolar Transistor IGBT with a Gate G forming a first electrode and an Emitter E forming a second electrode, or

at least one Metal-Oxide-Semiconductor Field-Effect Transistor MOSFET with a Gate G forming a first electrode and a Source S forming a second electrode;

said first electrode including a polysilicon material made in one piece,

said one-piece being made partly of a monitoring portion,

said monitoring portion including said polysilicon material and being in electrical contact with the second electrode such that a leakage current flows between the first electrode and the second electrode in an operational state of the module;

said monitoring portion having a location, a form, a size and a material composition selected together such that to have a variable resistance in function of its temperature during said operational state of said module,

characterized in that the monitoring portion comprises at least one of the following:

a polysilicon layer covering continuously at least a trench of the first electrode and a dummy trench of the second electrode;

an extension part of the second electrode disposed between a polysilicon material element of the first electrode and a polysilicon material element of the second electrode in such a way to ensure an electric link between said two electrodes.

2. Module according to claim 1 , wherein said monitoring portion have a material composition and a useful cross-section selected together such that:

a resistance value of the monitoring portion has a value between 10 kΩ and 1 MΩ for the expected operating temperatures range of the module; and/or

a resistance value of the monitoring portion has a variation of at least a factor of 2% within the expected operating temperatures range of the module.

3. Module according to claim 1 , wherein the monitoring portion comprises the following:

a passage arranged through an oxide layer lining a wall of a trench of the first electrode.

4. Module according to claim 1 , further comprising a measurement circuitry electrically connected between the first electrode and the second electrode.

5. Module according to claim 4 , wherein the measurement circuitry includes:

at least one Analog-to-Digital Converter;

a resistance having a resistance value Rm, Rm being equal to α×R, where R is the resistance of the monitoring portion and α is a factor comprised between 0.1 and 10; and

a set of switches arranged such that to connect and disconnect the resistance from a closed electrical network including the first electrode, the second electrode, and a voltage source of a gate driver.

6. A mask for a polysilicon deposition operation during fabrication of a module according to claim 1 , said mask being configured such that the polysilicon material forming the first electrode and the monitoring portion is deposited during a single deposition operation and in one piece.

7. A measurement method for estimating a temperature of a power semi-conductor module according to claim 1 ;

said method comprising:

a) trigger a measurement when no current is provided from the Emitter E of the Insulated Gate Bipolar Transistor IGBT, respectively from the Source S of the Metal-Oxide-Semiconductor Field-Effect Transistor MOSFET;

b) generate a diagnostic mode of the first electrode of the module during which a resistance is positioned in a closed electrical network including the first electrode, the second electrode, and a voltage source of a gate driver;

c) monitor at least a voltage or a current on said loop;

d) convert the monitored values into temperatures according to calibration data.

8. Computer software comprising instructions to implement the method according to claim 7 when the software is executed by a processor.

9. Computer-readable non-transient recording medium on which a software is registered to implement the method according to claim 7 when the software is executed by a processor.

10. A measurement method for estimating a state of health of a connection of a power semi-conductor module according to claim 1 ;

said method comprising:

1) trigger a measurement when a high current is crossing a connection of the Emitter E of the Insulated Gate Bipolar Transistor IGBT, respectively from the Source S of the Metal-Oxide-Semiconductor Field-Effect Transistor MOSFET;

2) generate a diagnostic mode of the first electrode of the module during which said first electrode is electrically disconnected;

3) monitor at least a voltage;

4) convert the monitored values into a damage index according to calibration data.

11. Computer software comprising instructions to implement the method according to claim 10 when the software is executed by a processor.

12. Computer-readable non-transient recording medium on which a software is registered to implement the method according to claim 10 when the software is executed by a processor.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 1, 2020
From: DEGRENNE, NICOLAS
To: MITSUBISHI ELECTRIC R&D CENTRE EUROPE B.V.
Reel/Frame 054507/0958 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 1, 2020
From: MITSUBISHI ELECTRIC R&D CENTRE EUROPE B.V.
To: MITSUBISHI ELECTRIC CORPORATION
Reel/Frame 054507/0975 →
Priority Claims (1)
EP 18305988 · Jul 19, 2018 · regional
Continuity (1)
Related Publication 20210223307A1 · Jul 22, 2021