Packaged electronic circuits having moisture protection encapsulation and methods of forming same

1. A packaged electronic circuit, comprising:

a substrate having an upper surface;

a first metal layer on the upper surface of the substrate;

a first dielectric layer on the first metal layer;

a first polymer layer on the first metal layer;

a second metal layer on the first polymer layer such that a portion of the first dielectric layer is between the first metal layer and the first polymer layer, and a portion of the first polymer layer is between the first dielectric layer and the second metal layer,

wherein the first metal layer, the first dielectric layer and the second metal layer form a capacitor.

2. The packaged electronic circuit of claim 1 , wherein the first polymer layer is between the first metal layer and a periphery of the second metal layer, and wherein the first polymer layer has a thickness in a direction perpendicular to the upper surface of the substrate that is greater than a thickness of the first dielectric layer.

3. The packaged electronic circuit of claim 2 , wherein the periphery of the second metal layer is spaced farther above the first metal layer than is a center of the second metal layer.

4. The packaged electronic circuit of claim 3 , wherein the first metal layer is coupled to a gate of a transistor.

5. The packaged electronic circuit of claim 1 , wherein the first polymer layer is not between a center of the second metal layer and the first metal layer.

6. The packaged electronic circuit of claim 1 , wherein the electronic circuit comprises a power amplifier integrated circuit chip having a unit cell transistor that includes a channel layer and a barrier layer, wherein the first metal layer comprises a source contact, and wherein the second metal layer comprises a gate jumper that is coupled between a gate electrode and a gate finger of a transistor.

7. The packaged electronic circuit of claim 1 , wherein the electronic circuit is an internally matched field effect transistor or a ceramic substrate or a printed circuit board that has capacitors and/or inductors formed thereon.

8. The packaged electronic circuit of claim 1 , further comprising:

a second dielectric layer on the first polymer layer and on at least a portion of the second metal layer; and

a second polymer layer on the second dielectric layer.

9. The packaged electronic circuit of claim 8 , wherein the first polymer layer directly contacts an upper surface of the first dielectric layer, the second dielectric layer directly contacts an upper surface of the first polymer layer, and the second polymer layer directly contacts an upper surface of the second dielectric layer.

10. The packaged electronic circuit of claim 8 , wherein the first polymer layer directly contacts the first metal layer, the second metal layer, the first dielectric layer, and the second dielectric layer.

11. The packaged electronic circuit of claim 1 , wherein the first polymer layer is between a first edge of the second metal layer and the first metal layer.

12. A packaged electronic circuit, comprising:

a substrate having an upper surface;

a first metal layer on the upper surface of the substrate;

a first polymer layer on the first metal layer opposite the substrate;

a second metal layer on the first polymer layer opposite the first metal layer;

a dielectric layer on the first polymer layer and at least a portion of the second metal layer; and

a second polymer layer on the dielectric layer,

wherein the second metal layer comprises a gate jumper that is coupled between a gate electrode and a gate finger of a transistor.

13. A packaged electronic circuit, comprising:

a substrate having an upper surface;

a first metal layer on the upper surface of the substrate;

a first polymer layer on the first metal layer opposite the substrate;

a second metal layer on the first polymer layer opposite the first metal layer;

a dielectric layer on the first polymer layer and at least a portion of the second metal layer; and

a second polymer layer on the dielectric layer,

wherein the first metal layer comprises a metal trace that includes self-coupling sections that have a substantially same instantaneous current direction.

14. A packaged electronic circuit, comprising:

a substrate having an upper surface;

a first metal layer on the upper surface of the substrate;

a first polymer layer on the first metal layer opposite the substrate;

a second metal layer on the first polymer layer opposite the first metal layer;

a dielectric layer on the first polymer layer and at least a portion of the second metal layer; and

a second polymer layer on the dielectric layer,

wherein the packaged electronic circuit is a monolithic microwave integrated circuit, and wherein a plurality of transistors are provided on the substrate, and wherein the dielectric layer is formed on upper surfaces of the transistors and the second polymer layer is not formed on the upper surfaces of the transistors.

15. A packaged electronic circuit, comprising:

a substrate having an upper surface;

a first metal layer on the upper surface of the substrate;

a first polymer layer on the first metal layer opposite the substrate;

a second metal layer on the first polymer layer opposite the first metal layer;

a first dielectric layer between the first metal layer and the second metal layer;

a second dielectric layer on the first polymer layer and at least a portion of the second metal layer; and

a second polymer layer on the second dielectric layer,

wherein the first dielectric layer comprises at least one of silicon oxide, silicon nitride and silicon oxynitride and the second dielectric layer comprises at least one of silicon oxide, silicon nitride and silicon oxynitride,

wherein the first polymer layer directly contacts the first metal layer, the second metal layer, the first dielectric layer, and the second dielectric layer.

16. A packaged electronic circuit, comprising:

a substrate having an upper surface;

a first metal layer on the upper surface of the substrate;

a first polymer layer on the first metal layer opposite the substrate;

a second metal layer on the first polymer layer opposite the first metal layer;

a first dielectric layer between the first metal layer and the second metal layer;

a second dielectric layer on the first polymer layer and at least a portion of the second metal layer; and

a second polymer layer on the second dielectric layer,

wherein the first dielectric layer comprises at least one of silicon oxide, silicon nitride and silicon oxynitride and the second dielectric layer comprises at least one of silicon oxide, silicon nitride and silicon oxynitride,

wherein the first dielectric layer is between the first metal layer and the first polymer layer, and the first polymer layer is between the first dielectric layer and the second metal layer.