Semiconductor device
The present disclosure provides a semiconductor device manufacturing method. The method includes: providing a semiconductor substrate, including a high-frequency-block group and a low-power-block group; forming high-frequency-type logic standard cells on the high-frequency-block group of the semiconductor substrate. The high-frequency-type logic standard cells have a high-frequency-type cell height, a high-frequency-type operating frequency, and a high-frequency-type power. The method further includes forming low-power-type logic standard cells on the low-power-block group of the semiconductor substrate. The low-power-type logic standard cells have a low-power-type cell height, a low-power-type operating frequency, and a low-power-type power.
1. A method of forming a semiconductor device, comprising:
providing a semiconductor substrate, including a high-frequency-block group and a low-power-block group;
forming high-frequency-type logic standard cells on the high-frequency-block group of the semiconductor substrate, wherein the high-frequency-type logic standard cells have a high-frequency-type cell height, a high-frequency-type operating frequency, and a high-frequency-type power; and
forming low-power-type logic standard cells on the low-power-block group of the semiconductor substrate, wherein the low-power-type logic standard cells have a low-power-type cell height, a low-power-type operating frequency, and a low-power-type power,
wherein the high-frequency-type cell height is greater than the low-power-type cell height, the high-frequency-type operating frequency is greater than the low-power-type operating frequency, and the high-frequency-type power is greater than the low-power-type power;
wherein forming the high-frequency-type logic standard cells includes: forming high-frequency-type fins on the high-frequency-block group of the semiconductor substrate; and
wherein forming the low-power-type logic standard cells includes: forming low-power-type fins on the low-power-block group of the semiconductor substrate, wherein an effective height of the high-frequency-type fins is greater than an effective height of the low-power-type fins, a fin arrangement density of the high-frequency-type fins in an arrangement direction of the high-frequency-type fins is greater than a fin arrangement density of the low-frequency-type fins in an arrangement direction of the high-frequency-type fins, the fin arrangement density of the high-frequency-type fins in the arrangement direction of the high-frequency-type fins is are sequentially decreased with the high-frequency-type operating frequency, and a fin arrangement density of the low-frequency-type fins in the arrangement direction of the low-frequency-type fins is sequentially decreasing with the low-frequency-type operating frequency.
2. The method according to claim 1 , wherein:
the high-frequency-block group includes a number of N mutually discrete high-frequency-blocks, numbered from a first high-frequency-block to an N th high-frequency-block, and N is an integer greater than or equal to 2;
the high-frequency-type logic standard cells are numbered from a first high-frequency-type logic standard cell to an N th high-frequency-type logic standard cell,
the first high-frequency-type logic standard cell is located on the first high-frequency-block of the semiconductor substrate, and has a first high-frequency-type cell height C h1 , a first high-frequency-type operating frequency f h1 , and a first high-frequency-type power P h1 ,
the N th high-frequency-type logic standard cell is located on the N th high-frequency-block of the semiconductor substrate, and has an N th high-frequency-type cell height C hN , an N th high-frequency-type operating frequency f hN , and an N th high-frequency-type power P hN ,
wherein high-frequency-type cell heights are sequentially decreased from C h1 to C hN , high-frequency-type operating frequencies are sequentially decreased from f h1 to f hN , and high-frequency-type powers are sequentially decreased from P h1 to P hN ; and
the first high-frequency-type logic standard cell includes first high-frequency-type fins on the first high-frequency-block of the semiconductor substrate, and the N th high-frequency-type logic standard cell includes N th high-frequency-type fins on the N th high-frequency-block of the semiconductor substrate, wherein effective heights are sequentially decreased from the first high-frequency-type fins to the N th high-frequency-type fins.
3. The method according to claim 2 , further comprising:
forming an isolation structure on the semiconductor substrate, wherein the isolation structure covers a portion of a sidewall of each high-frequency-type fin from the first high-frequency-type fins to the N th high-frequency-type fins, wherein:
the effective height of the first high-frequency-type fins is a distance from a top surface of the first high-frequency-type fins to a surface of the isolation structure, and
the effective height of the N th high-frequency-type fins is a distance from a top surface of the N th high-frequency-type fins to the surface of the isolation structure.
4. The method according to claim 2 , wherein:
an arrangement direction of the first high-frequency-type fins is parallel to an extending direction of the first high-frequency-type fins, and an arrangement direction of the N th high-frequency-type fins is parallel to an extending direction of the N th high-frequency-type fins;
in the arrangement direction of the first high-frequency-type fins, the first high-frequency-type fins have a first high-frequency-type fin arrangement density, and in the arrangement direction of the N th high-frequency-type fins, the N th high-frequency-type fins have an N th high-frequency-type fin arrangement density; and
high-frequency-type fin arrangement densities are sequentially decreased from the first high-frequency-type fin arrangement density to the N th high-frequency-type fin arrangement density.
5. The method according to claim 1 , wherein forming the isolation structure comprises:
forming isolation structure films on the high-frequency-block group and the low-power-block group of the semiconductor substrate, and on the high-frequency-type fins and the low-power-type fins of the semiconductor substrate, wherein:
the isolation structure films are etched back until a portion of the sidewall of each high-frequency-type fin from the high-frequency-type fins and a portion of the sidewall of each low-power-type fin from the low-power-type fins are exposed to form the isolation structure.
6. The method according to claim 5 , wherein:
the low-power-block group includes a number of M mutually discrete low-power-blocks, numbered from a first low-power-block to an M th low-power-block, and M is an integer greater than or equal to 2;
the low-power-type logic standard cells are numbered from a first low-power-type logic standard cell to an M th low-power-type logic standard cell,
the first low-power-type logic standard cell is located on the first low-power-block of the semiconductor substrate, and has a first low-power-type cell height C d1 , a first low-power-type operating frequency f d1 , and a first low-power-type power P d1 ,
the M th low-power-type logic standard cell is located on the M th low-power-block of the semiconductor substrate, and has an M th low-power-type cell height C dM , an M th low-power-type operating frequency f dM , and an M th low-power-type power P dM ,
wherein low-power-type cell heights are sequentially decreased from C d1 to C dM , low-power-type operating frequencies are sequentially decreased from f d1 to f dM , low-power-type powers are sequentially decreased from P d1 to P dM ; and
the first low-power-type logic standard cell includes first low-power-type fins located on the first low-power-block of the semiconductor substrate, and the M th low-power-type logic standard cell includes M th low-power-type fins located on the M th low-power-block of the semiconductor substrate, wherein effective heights are sequentially decreased from the first low-power-type fins to the M th low-power-type fins.
7. The method according to claim 6 , further comprising:
forming an isolation structure on the semiconductor substrate, wherein the isolation structure covers a portion of a sidewall of each first low-power-type fin from the first low-power-type fins to the M th low-power-type fins, wherein:
the effective height of the first low-power-type fins is a distance from a top surface of the first low-power-type fins to a surface of the isolation structure, and the effective height of the M th low-power-type fins is a distance from a top surface of the M th low-power-type fins to the surface of the isolation structure.
8. The method according to claim 6 , wherein:
an arrangement direction of the first low-power-type fins is parallel to an extending direction of the first low-power-type fins, and an arrangement direction of the M th low-power-type fins is parallel to an extending direction of the M th low-power-type fins;
in the arrangement direction of the first low-power-type fins, the first low-power-type fins have a first low-power-type fin arrangement density, and in the arrangement direction of the M th low-power-type fins, the M th low-power-type fins have an M th low-power-type fin arrangement density; and
low-power-type fin arrangement densities are sequentially decreased from the first low-power-type fin arrangement density to the M th low-power-type fin arrangement density.
9. The method according to claim 5 , wherein the isolation structure film of the low-power-block group is etched back during the process of etching back the isolation structure film of the high-frequency-block group.
10. The method according to claim 9 , wherein etching back the isolation structure films comprises: a Certas dry etching process, comprising a remote dry etching and an in-situ annealing after the remote dry etching, wherein:
parameters of the remote dry etching include: gases including HF and NH 3 , a flow rate of NH 3 of 50 sccm to 500 sccm, a flow rate of HF of 20 sccm to 300 sccm, a chamber pressure of 2000 mtorr to 5000 mtorr, and a temperature of 20° C. to 200° C., and
parameters of the in-situ annealing include: a temperature of 100° C. to 200° C.
11. The method according to claim 5 , wherein etching back the isolation structure films comprises:
etching back the isolation structure film of the low-power-block group after etching back the isolation structure film of the high-frequency-block group, or etching back the isolation structure film of the high-frequency-block group after etching back the isolation structure film of the low-power-block group.