Semiconductor structure
A semiconductor structure is provided. The semiconductor structure includes a base substrate including a plurality of non-device regions; a middle fin structure and an edge fin disposed around the middle fin structure on the base substrate between adjacent non-device regions; a first barrier layer on sidewalls of the edge fin; and an isolation layer on the base substrate. The isolation layer has a top surface lower than the edge fin and the middle fin structure, and covers a portion of the sidewalls of each of the edge fin and the middle fin structure. The isolation layer further has a material density smaller than the first barrier layer.
1. A semiconductor structure, comprising:
a base substrate, wherein the base substrate includes a plurality of non-device regions;
a middle fin structure and an edge fin disposed around the middle fin structure on the base substrate between adjacent non-device regions;
a first barrier layer on sidewalls of the edge fin; and
an isolation layer on the base substrate, wherein:
the isolation layer has a top surface lower than the edge fin and the middle fin structure, and covers a portion of the sidewalls of each of the edge fin and the middle fin structure;
the isolation layer has a material density smaller than the first barrier layer;
a non-device region has a first dimension in a direction perpendicular to the sidewall of the edge fin;
the edge fin is spaced apart by a second dimension from the sidewall of the middle fin structure, wherein the second dimension is smaller than the first dimension.
2. A semiconductor structure, comprising:
a base substrate, wherein the base substrate includes a plurality of non-device regions;
a middle fin structure and an edge fin disposed around the middle fin structure on the base substrate between adjacent non-device regions;
a first barrier layer on sidewalls of the edge fin; and
an isolation layer on the base substrate, wherein:
the isolation layer has a top surface lower than the edge fin and the middle fin structure, and covers a portion of the sidewalls of each of the edge fin and the middle fin structure;
the isolation layer has a material density smaller than the first barrier layer
a non-device region has a first dimension in a direction perpendicular to the sidewall of the edge fin;
the edge fin is spaced apart by a second dimension from the sidewall of the middle fin structure, wherein the second dimension is smaller than the first dimension;
the first dimension is above 56 nm; and
the second dimension is in a range of approximately 32 nm-40 nm.
3. The semiconductor structure according to claim 1 , wherein:
the edge fin has a dimension in a range of approximately 6 nm-10 nm in a direction perpendicular to the sidewall of the edge fin.
4. The semiconductor structure according to claim 1 , wherein:
the first barrier layer is made of one of silicon oxide and silicon nitride.
5. The semiconductor structure according to claim 1 , wherein:
the first barrier layer has a thickness in a range of approximately 1.5 nm-6 nm.
6. The semiconductor structure according to claim 1 , wherein:
the isolation layer is made of silicon oxide.
7. The semiconductor structure according to claim 1 , further including:
a gate structure across the edge fin and the middle fin structure; and
source and drain doped regions in the edge fin and the middle fin structure on both sides of the gate structure, respectively.
8. The semiconductor structure according to claim 1 , further including:
a second barrier layer on the base substrate, wherein the second barrier layer covers the sidewall surfaces of the edge fin and the sidewall and top surfaces of the middle fin structure.
9. The semiconductor structure according to claim 8 , wherein:
the second barrier layer isolates the base substrate and the middle fin structure from the isolation layer;
the second barrier layer further isolates the first barrier layer from the isolation layer.
10. The semiconductor structure according to claim 8 , wherein:
the second barrier layer is made of one of silicon oxide, silicon nitride, and amorphous silicon.
11. The semiconductor structure according to claim 8 , wherein:
the second barrier layer has a thickness in a range of approximately 2 nm-8 nm.
12. The semiconductor structure according to claim 2 , wherein:
the edge fin has a dimension in a range of approximately 6 nm-10 nm in a direction perpendicular to the sidewall of the edge fin.
13. The semiconductor structure according to claim 2 , wherein:
the first barrier layer is made of one of silicon oxide and silicon nitride.
14. The semiconductor structure according to claim 2 , wherein:
the first barrier layer has a thickness in a range of approximately 1.5 nm-6 nm.
15. The semiconductor structure according to claim 2 , wherein:
the isolation layer is made of silicon oxide.
16. The semiconductor structure according to claim 2 , further including:
a gate structure across the edge fin and the middle fin structure; and
source and drain doped regions in the edge fin and the middle fin structure on both sides of the gate structure, respectively.
17. The semiconductor structure according to claim 2 , further including:
a second barrier layer on the base substrate, wherein the second barrier layer covers the sidewall surfaces of the edge fin and the sidewall and top surfaces of the middle fin structure.
18. The semiconductor structure according to claim 17 , wherein:
the second barrier layer isolates the base substrate and the middle fin structure from the isolation layer;
the second barrier layer further isolates the first barrier layer from the isolation layer.
19. The semiconductor structure according to claim 17 , wherein:
the second barrier layer is made of one of silicon oxide, silicon nitride, and amorphous silicon.
20. The semiconductor structure according to claim 17 , wherein:
the second barrier layer has a thickness in a range of approximately 2 nm-8 nm.