Pixel circuit and display apparatus having the same

1. A pixel circuit comprising:

a first switching element comprising a control electrode connected to a first node, an input electrode which receives a first power voltage and an output electrode connected to a third node;

a second switching element comprising a control electrode which receives a compensation gate signal, an input electrode connected to a second node and an output electrode connected to the third node;

a third switching element comprising a control electrode which receives a write gate signal, an input electrode connected to the first node and an output electrode connected to the second node;

a storage capacitor comprising a first electrode which receives an initialization voltage and a second electrode connected to the first node;

a program capacitor comprising a first electrode which receives a data voltage and a second electrode connected to the second node; and

an organic light emitting element comprising a first electrode connected to the third node and a second electrode which receives a second power voltage.

2. The pixel circuit of claim 1 , wherein the first switching element, the second switching element and the third switching element are P-type transistors.

3. The pixel circuit of claim 2 , wherein, during an on bias period, the first switching element is turned on, the second switching element is turned off, the third switching element is turned off, the first power voltage has a high level, the second power voltage has a high level, and the initialization voltage has a low level.

4. The pixel circuit of claim 3 , wherein, during an initialization period subsequent to the on bias period, the first switching element is turned on, the second switching element is turned on, the third switching element is turned on, the first power voltage has a low level, the second power voltage has the high level, and the initialization voltage has the low level.

5. The pixel circuit of claim 4 , wherein, during a threshold voltage compensation period subsequent to the initialization period, the first switching element is turned on, the second switching element is turned on, the third switching element is turned on, the first power voltage has the high level, the second power voltage has the high level, and the initialization voltage has a high level.

6. The pixel circuit of claim 5 , wherein, during a programming period subsequent to the threshold voltage compensation period, the first switching element is turned on, the second switching element is turned off, the third switching element is turned on, the first power voltage has the low level, the second power voltage has the high level, and the initialization voltage has the high level.

7. The pixel circuit of claim 6 , wherein, during a pre-emission anode initialization period subsequent to the programming period, the first switching element is turned on, the second switching element is turned off, the third switching element is turned off, the first power voltage has the low level, the second power voltage has the high level, and the initialization voltage has the low level.

8. The pixel circuit of claim 7 , wherein, during an emission period subsequent to the pre-emission anode initialization period, the first switching element is turned on, the second switching element is turned off, the third switching element is turned off, the first power voltage has the high level, the second power voltage has the low level, and the initialization voltage has the high level.

9. The pixel circuit of claim 3 ,

wherein, during a first initialization period subsequent to the on bias period, the first switching element is turned on, the second switching element is turned on, the third switching element is turned off, the first power voltage has a low level, the second power voltage has the high level, and the initialization voltage has the low level, and

wherein, during a second initialization period subsequent to the first initialization period, the first switching element is turned on, the second switching element is turned on, the third switching element is turned on, the first power voltage has the low level, the second power voltage has the high level, and the initialization voltage has the low level.

10. The pixel circuit of claim 3 ,

wherein during an initialization period subsequent to the on bias period, the first switching element is turned on, the second switching element is turned on, the third switching element is turned on, the first power voltage has a low level, the second power voltage has the high level, and the initialization voltage has the low level, and

wherein the initialization voltage temporarily has a high level at a boundary between the on bias period and the initialization period.

11. The pixel circuit of claim 3 ,

wherein during a first initialization period subsequent to the on bias period, the first switching element is turned on, the second switching element is turned on, the third switching element is turned off, the first power voltage has a low level, the second power voltage has the high level, and the initialization voltage has the low level,

wherein during a second initialization period subsequent to the first initialization period, the first switching element is turned on, the second switching element is turned on, the third switching element is turned on, the first power voltage has the low level, the second power voltage has the high level, and the initialization voltage has the low level, and

wherein the initialization voltage temporarily has a high level at a boundary between the on bias period and the first initialization period.

12. The pixel circuit of claim 2 , wherein the compensation gate signal is a write gate signal of a different pixel.

13. The pixel circuit of claim 1 , wherein the first switching element, the second switching element and the third switching element are N-type transistors.

14. The pixel circuit of claim 13 , wherein during an initialization period, the first switching element is turned on, the second switching element is turned on, the third switching element is turned on, and the first power voltage has an intermediate level between a high level and a low level.

15. The pixel circuit of claim 14 , wherein, during a threshold voltage compensation period subsequent to the initialization period, the first switching element is turned on, the second switching element is turned on, the third switching element is turned on, the first power voltage has the low level, and the initialization voltage has a low level.

16. The pixel circuit of claim 15 , wherein, during a programming period subsequent to the threshold voltage compensation period, the first switching element is turned on, the second switching element is turned off, the third switching element is turned on, the first power voltage has the high level, and the initialization voltage has the low level.

17. The pixel circuit of claim 16 , wherein, during an emission period subsequent to the programming period, the first switching element is turned on, the second switching element is turned off, the third switching element is turned off, the first power voltage has the high level, and the initialization voltage has a high level.

18. The pixel circuit of claim 13 , wherein the compensation gate signal is a write gate signal of a different pixel.

19. The pixel circuit of claim 1 ,

wherein the first switching element is a P-type transistor, and

wherein the second switching element and the third switching element are N-type transistors.

20. A display apparatus comprising:

a display panel comprising a plurality of pixels;

a gate driver which outputs a write gate signal to the pixels; and

a data driver which outputs a data voltage to the pixels,

wherein a pixel of the pixels comprises:

a first switching element comprising a control electrode connected to a first node, an input electrode which receives a first power voltage and an output electrode connected to a third node;

a second switching element comprising a control electrode which receives a compensation gate signal, an input electrode connected to a second node and an output electrode connected to the third node;

a third switching element comprising a control electrode which receives the write gate signal, an input electrode connected to the first node and an output electrode connected to the second node;

a storage capacitor comprising a first electrode which receives an initialization voltage and a second electrode connected to the first node;

a program capacitor comprising a first electrode which receives the data voltage and a second electrode connected to the second node; and

an organic light emitting element comprising a first electrode connected to the third node and a second electrode which receives a second power voltage.