Diffusion barrier layer for source and drain structures to increase transistor performance

1. A method for manufacturing an integrated chip, the method comprising:

forming a gate electrode structure over a semiconductor substrate;

forming a diffusion barrier layer over the semiconductor substrate and laterally adjacent to the gate electrode structure, wherein the diffusion barrier layer comprises a barrier dopant; and

forming an epitaxial source/drain layer over the diffusion barrier layer such that the epitaxial source/drain layer comprises a first dopant different from the barrier dopant, wherein the diffusion barrier layer is between the epitaxial source/drain layer and the semiconductor substrate, wherein the diffusion barrier layer is co-doped with the barrier dopant and the first dopant.

2. The method of claim 1 , wherein forming the diffusion barrier layer includes:

forming a masking layer over the semiconductor substrate, wherein the masking layer comprises a plurality of sidewalls defining source/drain region opening over the semiconductor substrate; and

performing a selective epitaxial growth process to selectively form the diffusion barrier layer within the source/drain region opening, wherein the selective epitaxial growth process includes in-situ doping the diffusion barrier layer with the first dopant and the barrier dopant.

3. The method of claim 2 , wherein the diffusion barrier layer is formed such that a doping profile of the barrier dopant within the diffusion barrier layer has a gaussian distribution.

4. The method of claim 1 , wherein forming the epitaxial source/drain layer includes performing a selective epitaxial growth process to selectively form the epitaxial source/drain layer along a top surface of the diffusion barrier layer, wherein a bottom surface of the epitaxial source/drain layer is vertically above a top surface of the semiconductor substrate.

5. The method of claim 1 , wherein a doping concentration of the barrier dopant within the diffusion barrier layer is less than a doping concentration of the first dopant within the diffusion barrier layer.

6. The method of claim 1 , wherein the diffusion barrier layer is formed to a first thickness and the epitaxial source/drain layer is formed to a second thickness greater than the first thickness.

7. The method of claim 1 , wherein forming the diffusion barrier layer includes flowing a barrier dopant precursor gas over the semiconductor substrate at a constant rate.

8. The method of claim 1 , wherein the diffusion barrier layer is formed at a temperature within a range of about 500° Celsius and 650° Celsius, wherein the diffusion barrier layer is formed at a pressure within a range of about 10 Tor to 300 Tor.

9. A method for manufacturing an integrated chip, the method comprising:

forming a first gate electrode structure over a semiconductor substrate, wherein the semiconductor substrate comprises a first semiconductor layer, a second semiconductor layer, and an insulating layer disposed between the first and second semiconductor layers;

forming a first pair of epitaxial source/drain layers on the first semiconductor layer and on opposing sides of the first gate electrode structure;

forming a second gate electrode structure over the first semiconductor layer and laterally offset from the first gate electrode structure;

forming a second pair of epitaxial source/drain layers on the first semiconductor layer and on opposing sides of the second gate electrode structure; and

forming diffusion barrier layers between the first semiconductor layer and the first pair of epitaxial source/drain layers, wherein a top surface of the diffusion barrier layers is disposed at or above a top surface of the first semiconductor layer, wherein forming the diffusion barrier layers comprises flowing a carrier gas, a silicon precursor gas, a first dopant precursor gas, and a barrier dopant precursor gas over the first semiconductor layer.

10. The method of claim 9 , wherein the first pair of epitaxial source/drain layers comprise an N-type dopant and the second pair of epitaxial source/drain layers comprise a P-type dopant.

11. The method of claim 10 , wherein the diffusion barrier layers comprise a barrier dopant different than the N-type dopant and the P-type dopant.

12. The method of claim 9 , further comprising:

forming a plurality of silicide layers over the first pair of epitaxial source/drain layers and the second pair of epitaxial source/drain layers.

13. The method of claim 9 , wherein sidewalls of the diffusion barrier layers are aligned with sidewalls of the first pair of epitaxial source/drain layers.

14. The method of claim 9 , wherein the barrier dopant precursor gas is flowed over the first semiconductor layer at a constant rate such that a doping profile of a barrier dopant within the diffusion barrier layers has a gaussian distribution.

15. The method of claim 9 , wherein the barrier dopant precursor gas is flowed over the first semiconductor layer at a gradually decreasing rate such that a doping profile of a barrier dopant within the diffusion barrier layers has a gradient distribution.

16. A method for manufacturing an integrated chip, the method comprising:

forming an N-type gate structure over a semiconductor substrate,

selectively depositing a first pair of epitaxial source/drain layers on the semiconductor substrate and on opposing sides of the N-type gate structure, wherein the first pair of epitaxial source/drain layers comprises an N-type dopant, wherein the first pair of epitaxial source/drain layers has a first thickness; and

selectively depositing a pair of diffusion barrier layers below the first pair of epitaxial source/drain layers, wherein the pair of diffusion barrier layers comprise the N-type dopant and a first dopant, wherein the pair of diffusion barrier layers directly contacts a bottom surface of the first pair of epitaxial source/drain layers, and wherein the pair of diffusion barrier layers has a second thickness less than the first thickness.

17. The method of claim 16 , further comprising:

forming a sidewall spacer structure around the N-type gate structure, wherein the pair of diffusion barrier layers is separated from the N-type gate structure by the sidewall spacer structure.

18. The method of claim 16 , wherein the bottom surface of the first pair of epitaxial source/drain layers is vertically above a top surface of the semiconductor substrate.

19. The method of claim 1 , wherein a doping concentration of the first dopant within the epitaxial source/drain layer is greater than a doping concentration of the first dopant within the diffusion barrier layer.

20. The method of claim 9 , wherein the diffusion barrier layers comprise silicon, carbon, and phosphorus.