Reconfigurable series-shunt LDO

1. A low-dropout regulator comprising:

a core circuitry providing an output voltage to an output node; and

a reverse isolation circuitry coupled to the output node and configured to

provide a current flowing through the reverse isolation circuitry in response to ripples at the output node,

wherein the core circuitry comprises a first transistor coupled to the output node, the first transistor being coupled between the output node and a ground node,

wherein the reverse isolation circuitry comprises a second transistor coupled to the output node and having a second gate node controlled by a gate voltage, wherein the gate voltage additionally controls a first gate node of the first transistor.

2. The low-dropout regulator of claim 1 , wherein

the reverse isolation circuitry is configured with bandwidth higher than that of the core circuitry such that the reverse isolation circuitry responds to the ripples at the output node faster than the core circuitry.

3. The low-dropout regulator of claim 1 , wherein

the reverse isolation circuitry is configured such that a current flowing through the core circuitry is constant regardless the ripples at the output node or an alternating current (AC) component of the current flowing through the core circuitry is smaller than an AC component required to respond to the ripples at the output node.

4. The low-dropout regulator of claim 1 , wherein

the reverse isolation circuitry adjusts the current flowing through the reverse isolation circuitry based on a magnitude of the ripples at the output node.

5. The low-dropout regulator of claim 1 , wherein the gate voltage is generated based at least in part on the output voltage at the output node.

6. The low-dropout regulator of claim 5 , wherein

the second transistor comprises a plurality of transistors connected in parallel.

7. The low-dropout regulator of claim 1 , wherein

the first transistor is a pass transistor receiving a power supply voltage to generate the output voltage at the output node.

8. The low-dropout regulator of claim 1 , wherein the core circuitry comprises

a direct current (DC) circuitry coupled to the output node and comprising a power transistor configured to provide the output voltage at the output node, and

a power-supply rejection ratio (PSRR) circuitry coupled to the output node and configured to provide a high PSRR.

9. The low-dropout regulator of claim 7 , wherein the PSRR circuitry comprises

an operational amplifier configured to provide the gate voltage based at least in part on the output voltage at the output node, and

a capacitor coupled to the gate voltage.

10. A low-dropout regulator comprising:

a core circuitry providing an output voltage to an output node; and

a reverse isolation circuitry coupled to the output node and configured to

adjust a current flowing through the reverse isolation circuitry in response to ripples at the output node,

wherein the core circuitry comprises a first transistor coupled to the output node, the first transistor being coupled between the output node and a ground node,

wherein the reverse isolation circuitry comprises a second transistor coupled to the output node and having a second gate node controlled by a gate voltage, wherein the gate voltage additionally controls a first gate node of the first transistor.

11. The low-dropout regulator of claim 10 , wherein

the current flowing through the reverse isolation circuitry is adjusted at least in part to trade off between power consumed by the reverse isolation circuitry and a leakage current flowing through the core circuitry.

12. The low-dropout regulator of claim 10 , wherein

the reverse isolation circuitry comprises a plurality of transistors connected in parallel, and

one or more of the plurality of transistors are turned on depending on a tradeoff between power consumed by the reverse isolation circuitry and a leakage current flowing through the core circuitry.

13. The low-dropout regulator of claim 10 , wherein the gate voltage is generated based at least in part on the output voltage at the output node.

14. The low-dropout regulator of claim 10 , wherein

the first transistor is a pass transistor receiving a power supply voltage to generate the output voltage at the output node.

15. The low-dropout regulator of claim 10 , wherein the core circuitry comprises

a direct current (DC) circuitry coupled to the output node and comprising a power transistor configured to provide the output voltage at the output node, and

a power-supply rejection ratio (PSRR) circuitry coupled to the output node and configured to provide a high PSRR.

16. The low-dropout regulator of claim 15 , wherein the PSRR circuitry comprises

an operational amplifier configured to provide the gate voltage based at least in part on the output voltage at the output node, and

a capacitor coupled to the gate voltage.

17. The low-dropout regulator of claim 16 , wherein the core circuitry comprises

a decrease gain circuitry coupled to the output node and configured to reduce a gain of the DC circuitry.

18. A low-dropout regulator comprising:

a core circuitry configured to provide an output voltage to an output node; and

a reverse isolation circuitry coupled to the output node and configured to provide a current flowing through the reverse isolation circuitry, wherein the current flowing through the reverse isolation circuitry is configurable and/or reconfigurable,

wherein the core circuitry comprises a first transistor coupled to the output node, the first transistor being coupled between the output node and a ground node,

wherein the reverse isolation circuitry comprises a second transistor coupled to the output node and having a second gate node controlled by a gate voltage, wherein the gate voltage additionally controls a first gate node of the first transistor.