Semiconductor integrated circuit device
The present disclosure attempts to provide a capacitor cell having a large capacitance value per unit area in a semiconductor integrated circuit device using a three-dimensional transistor device. A logic cell includes a three-dimensional transistor device. A capacitor cell includes a three-dimensional transistor device. A length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the capacitor cell is greater than a length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the logic cell.
1. A semiconductor integrated circuit device comprising:
a standard cell which is a capacitor cell, wherein
the standard cell includes:
a first power supply interconnect (VDD) extending in a first direction and supplying a first power supply voltage;
a second power supply interconnect (VSS) extending in the first direction and supplying a second power supply voltage;
a capacitor provided between the first power supply interconnect and the second power supply interconnect, and including a three-dimensional transistor device;
a first interconnect ( 51 ) supplying the second power supply voltage; and
a second interconnect ( 52 ) supplying the first power supply voltage,
the first and second power supply interconnects are provided in a first metal interconnect layer,
the first interconnect includes:
a first portion ( 51 a ) extending in the first direction and adjacent to the first power supply interconnect, the first portion being an interconnect closest to the first power supply interconnect in the first metal interconnect layer;
a second portion ( 51 b ) extending in the first direction, the second portion being provided in the first metal interconnect layer; and
a third portion extending in a second direction perpendicular to the first direction and connecting the first portion and the second portion together, and
the second interconnect includes:
a fourth portion ( 52 a ) extending in the first direction and arranged on an opposite side of the first portion of the first interconnect from the first power supply interconnect in the first metal interconnect layer, the fourth portion of the second interconnect and the first portion of the first interconnect being adjacent to each other.
2. The semiconductor integrated circuit device of claim 1 , wherein
the second interconnect further includes:
a fifth portion extending in the second direction and connected to the fourth portion.
3. The semiconductor integrated circuit device of claim 2 , wherein
the second interconnect further includes:
a sixth portion extending in the first direction and connected to the fifth portion.
4. The semiconductor integrated circuit device of claim 1 , wherein
an interval between the first portion of the first interconnect and the first power supply interconnect, and an interval between the first portion of the first interconnect and the fourth portion of the second interconnect are equal to each other.
5. The semiconductor integrated circuit device of claim 1 , wherein
the three-dimensional transistor device is a fin field effect transistor (fin FET) or a nanowire FET.