Substrate structure, semiconductor package structure and method for manufacturing a substrate structure

1. A semiconductor package structure, comprising:

a substrate structure, comprising:

a first passivation layer having a first surface and a second surface opposite to the first surface;

a first circuit layer having a first portion disposed adjacent to the second surface of the first passivation layer and having an outer lateral surface; and

a first protection layer disposed on a second portion of the first circuit layer and exposed from the first surface of the first passivation layer;

a first semiconductor die disposed on the second surface of the first passivation layer;

a first encapsulant covering the first semiconductor die and the second surface of the first passivation layer, wherein there is a predetermined distance between the outer lateral surface of the first circuit layer and a lateral surface of the first encapsulant; and

a second semiconductor die disposed on the first surface of the first passivation layer;

a second encapsulant encapsulating the second semiconductor die, wherein the second encapsulant is surrounded by the second portion of the first circuit layer, wherein the second encapsulant has a surface substantially coplanar with the first protection layer.

2. The semiconductor package structure of claim 1 , wherein the substrate structure further comprises:

a core substrate disposed between the first passivation layer and the first semiconductor die;

a second passivation layer spaced apart from the first passivation layer by the core substrate; and

a second circuit layer spaced apart from and electrically connected to the first circuit layer; and

a second protection layer disposed on the second circuit layer wherein the second protection layer covers the first encapsulant.

3. A method of manufacturing a substrate structure, comprising:

(a) forming a first circuit layer, wherein the first circuit layer comprises a first portion and a second portion;

(b) forming a first passivation layer covering the first portion of the first circuit layer, wherein the second portion of the first circuit layer is exposed from the first passivation layer;

(c) forming a first protection layer on the second portion of the first circuit layer; and

(d) sawing the first passivation layer such that an outer lateral surface of the first circuit layer is covered by the first passivation layer or the first protection layer;

wherein before (a), the method further comprises:

(a1) providing a carrier, wherein a conductive foil is disposed on the carrier,

wherein in (a), the first circuit layer is formed on the conductive foil and exposes a portion of the conductive foil,

wherein in (b), the first passivation layer covers the portion of the conductive foil; and wherein after (d), the method further comprises:

(e) removing the carrier; and

(e1) removing the conductive foil from the first circuit layer and the first passivation layer.

4. The semiconductor package structure of claim 1 , wherein the lateral surface of the first encapsulant is substantially coplanar with the outer lateral surface of the first passivation layer.

5. The semiconductor package structure of claim 4 , wherein the lateral surface of the first encapsulant is substantially coplanar with the first protection layer.

6. The semiconductor package structure of claim 1 , further comprising:

a solder disposed on the first protection layer, wherein the solder is configured to correspond to a bonding pad of a carrier, wherein after the solder is bonded to the bonding pad, the solder exceeds an outer lateral surface of the first encapsulant.

7. The semiconductor package structure of claim 6 , wherein after the solder is bonded to the bonding pad, the solder is tapered along a direction from the first surface toward the second surface of the first passivation layer.

8. The method of claim 3 , wherein in (d) further comprises:

sawing the first protection layer.