System and method for a super-resolution digital-to-analog converter based on redundant sensing
A digital-to-analog converter device including a set of components, each component included in the set of components including a number of unit cells, each unit cell being associated with a unit cell size indicating manufacturing specifications of the unit cell is provided by the present disclosure. The digital-to-analog converter device further includes a plurality of switches, each switch included in the plurality of switches being coupled to a component included in the set of components, and an output electrode coupled to the plurality of switches. The digital-to-analog converter device is configured to output an output signal at the output electrode. A first unit cell size associated with a first unit cell included in the set of components is different than a second unit cell size associated with a second unit cell included in the set of components.
1. A digital-to-analog converter device comprising:
a set of components, each component included in the set of components comprising a number of unit cells and at least one component including a number of unit cells that is not a power of two;
a plurality of switches, each switch included in the plurality of switches being coupled to a component included in the set of components;
an output electrode coupled to the plurality of switches, the digital-to-analog converter device being configured to output an output signal at the output electrode; and
a controller coupled to the plurality of switches and configured to:
receive a desired output current;
determine an anodic component configuration comprising at least one component included in the set of components based on the desired output current;
determine a cathodic component configuration comprising at least one component included in the set of components based on the desired output current; and
cause a current pulse to be output at the output electrode based on the anodic component configuration and the cathodic component configuration.
2. The digital-to-analog converter device of claim 1 , wherein the current pulse includes a positive current pulse and a negative current pulse.
3. The digital-to-analog converter device of claim 1 , wherein the controller comprises a memory comprising a set of positive current values and negative current values associated with a set of component configurations, the anodic component configuration and the cathodic component configuration being included in the set of component configurations.
4. The digital-to-analog converter device of claim 1 , wherein the anodic component configuration includes at least one component not included in the cathodic component configuration.
5. The digital-to-analog converter device of claim 1 , wherein an effective resolution of the digital-to-analog converter device is at least four times greater than an intrinsic resolution of the digital-to-analog converter device.
6. The digital-to-analog converter device of claim 5 , wherein the effective resolution of the digital-to-analog converter device is equal to a Shannon entropy of the digital-to-analog converter device, and the intrinsic resolution is equal to log base two of the number of unit cells plus one.
7. The digital-to-analog converter device of claim 1 , wherein the digital-to-analog converter device is included in a neurostimulator device.
8. The digital-to-analog converter device of claim 1 , wherein a first unit cell size associated with a first unit cell included in the set of components is different than a second unit cell size associated with a second unit cell included in the set of components, the first unit cell size comprising a length and width of the first unit cell.
9. The digital-to-analog converter device of claim 8 , wherein the first unit cell size and the second unit cell size are associated with a transistor process size.
10. The digital-to-analog converter device of claim 1 , wherein each unit cell comprises at least one transistor.
11. The digital-to-analog converter device of claim 1 , wherein an effective resolution of the digital-to-analog converter device is at least two hundred times greater than an intrinsic resolution of the digital-to-analog converter device for at least ninety-five percent of a sample space of the digital-to-analog converter device.