Semiconductor integrated circuit device
A semiconductor integrated circuit device includes a standard cell having a plurality of height regions. A plurality of partial circuits having an identical function and each operating in response to common signals S and NS are arranged in any one of the height regions. A metal interconnect forming part of a supply path for the common signal S is arranged in the height region so as to be connected to the partial circuits, and a metal interconnect forming part of a supply path for the common signal S is arranged in the height region so as to be connected to the partial circuits.
1. A semiconductor integrated circuit device comprising a standard cell, wherein
the standard cell includes
N power supply lines (where N is an integer equal to or greater than three) including at least one first power supply line supplying a first power supply potential and at least one second power supply line supplying a second power supply potential, the first and second power supply lines extending in a first direction, and being alternately arranged in a second direction perpendicular to the first direction, and
M height regions (where M=N−1) each sandwiched between one of the at least one first power line and one of the at least one second power line, and
a plurality of flip-flop circuits each operating in response to one or more common signals,
in each of first height regions, which are at least two of the M height regions, a metal interconnect for a supply path for a first common signal, which is one of the common signals, is arranged and connected to at least two of the flip-flop circuits, the metal interconnect extending in the first direction.
2. The semiconductor integrated circuit device of claim 1 , wherein
the standard cell includes a common signal generating circuit generating the first common signal.
3. The semiconductor integrated circuit device of claim 1 , wherein
the supply path for the first common signal includes a gate interconnect extending in the second direction over two or more adjacent one of the M height regions.
4. The semiconductor integrated circuit device of claim 1 , wherein
the first common signal is a clock signal.
5. A semiconductor integrated circuit device comprising a standard cell, wherein
the standard cell includes
to N power supply lines (where N is an integer equal to or greater than three) including at least one first power supply line supplying a first power supply potential and at least one second power supply line supplying a second power supply potential, the first and second power supply lines extending in a first direction, and being alternately arranged in a second direction perpendicular to the first direction, and
M height regions (where M=N−1) each sandwiched between one of the at least one first power line and one of the at least one second power line, and
a plurality of flip-flop circuits each operating in response to at least two common signals,
in each of first height regions, which are at least two of the M height regions, a first metal interconnect for a supply path for a first common signal, which is one of the common signals, is arranged and connected to at least two of the flip-flop circuits, and
in each of second height regions, which are at least two of the M height regions, a second metal interconnect for a supply path for a second common signal, which is another of the common signals, is arranged and connected to at least two of the flip-flop circuits.
6. The semiconductor integrated circuit device of claim 5 , wherein
the standard cell includes a common signal generating circuit generating the first and second common signals.
7. The semiconductor integrated circuit device of claim 5 , wherein
the supply path for the first common signal includes a gate interconnect extending in the second direction over two or more adjacent one of the M height regions.
8. The semiconductor integrated circuit device of claim 5 , wherein
to the first common signal is a clock signal and the second common signal is an inverted clock signal which is an inverted signal of the clock signal.
9. The semiconductor integrated circuit device of claim 5 , wherein
the first and second metal interconnects extend in the first direction.
10. The semiconductor integrated circuit device of claim 5 , wherein
the second height regions are different from the first height regions.
11. The semiconductor integrated circuit device of claim 5 , wherein
the M height regions include the first height regions and the second height regions alternately arranged in the second direction.
12. A semiconductor integrated circuit device comprising a standard cell, wherein
the standard cell includes
N power supply lines (where N is an integer equal to or greater than three) including at least one first power supply line supplying a first power supply potential and at least one second power supply line supplying a second power supply potential, the first and second power supply lines extending in a first direction and formed in a first interconnect layer, and being alternately arranged in a second direction perpendicular to the first direction, and
M height regions (where M=N−1) each sandwiched between one of the at least one first power line and one of the at least one second power line, and
a plurality of flip-flop circuits each operating in response to one or more common signals,
in each of first height regions, which are at least two of the M height regions, a first metal interconnect for a supply path for a first common signal, which is one of the common signals, is arranged and connected to at least two of the flip-flop circuits, the first metal interconnect extending in the first direction and being formed in the first interconnect layer.
13. The semiconductor integrated circuit device of claim 12 , wherein
the standard cell includes a common signal generating circuit generating the first common signal.
14. The semiconductor integrated circuit device of claim 12 , wherein
the supply path for the first common signal includes a gate interconnect extending in the second direction over two or more adjacent one of the M height regions.
15. The semiconductor integrated circuit device of claim 12 , wherein
the first common signal is a clock signal.
16. The semiconductor integrated circuit device of claim 15 , wherein
the common signals include an inverted clock signal, which is an inverted signal of the clock signal,
in a second height region, which is at least one of the M height regions, a second metal interconnect for a supply path for the inverted clock signal is arranged and connected to at least two of the flip-flop circuits, the second metal interconnect extending in the first direction and being formed in the first interconnect layer.
17. The semiconductor integrated circuit device of claim 16 , wherein
the second height region is a height region different from the first height regions.
18. The semiconductor integrated circuit device of claim 17 , wherein
the M height regions include the first height regions and the second height region alternately arranged in the second direction.