Dummy FIN profile control to enlarge gate process window

1. A method comprising:

forming isolation regions extending into a semiconductor substrate, wherein semiconductor strips are located between the isolation regions;

forming a dielectric dummy strip between the isolation regions;

recessing the isolation regions, so that some portions of the semiconductor strips protrude higher than top surfaces of the recessed isolation regions to form protruding semiconductor fins, and a portion of the dielectric dummy strip protrudes higher than the top surfaces of the recessed isolation regions to form a dielectric dummy fin;

etching the dielectric dummy fin so that a top width of the dielectric dummy fin is smaller than a bottom width of the dielectric dummy fin; and

forming a gate stack on top surfaces and sidewalls of the protruding semiconductor fins and the dielectric dummy fin.

2. The method of claim 1 , wherein during the etching the dielectric dummy strip, the protruding semiconductor fins are exposed to an etching chemical used for the etching.

3. The method of claim 1 , wherein during the etching the dielectric dummy strip, the protruding semiconductor fins are protected by an etching mask.

4. The method of claim 1 further comprising:

etching the gate stack to form an opening, wherein the opening separates the gate stack into two portions, and the dielectric dummy fin is underlying and revealed through the opening; and

filling a dielectric material into the opening to form a gate isolation region.

5. The method of claim 4 further comprising:

removing the two portions of the gate stack to form trenches; and

forming replacement gate stacks in the trenches.

6. The method of claim 1 further comprising:

replacing the gate stack with a replacement gate stack;

etching the replacement gate stack to form an opening that separates the replacement gate stack into two portions, and the dielectric dummy fin is underlying and revealed through the opening; and

filling a dielectric material into the opening to form a gate isolation region.

7. The method of claim 1 , wherein before the etching the dielectric dummy fin, the top width of the dielectric dummy fin is greater than the bottom width of the dielectric dummy fin, and the top width is reduced by the etching the dielectric dummy fin more than the bottom width.

8. The method of claim 1 , wherein before the etching the dielectric dummy fin, the top width of the dielectric dummy fin is equal to the bottom width of the dielectric dummy fin, and the top width is reduced by the etching the dielectric dummy fin more than the bottom width.

9. The method of claim 1 , wherein the etching the dielectric dummy fin is performed using a dry etching process.

10. The method of claim 1 , wherein the etching the dielectric dummy fin is performed using a wet etching process.

11. The method of claim 1 , wherein after the etching, the dielectric dummy fin has a tapered profile with upper portions narrower than respective lower portions.

12. A device comprising:

a semiconductor substrate;

isolation regions over a bulk portion of the semiconductor substrate;

a semiconductor fin protruding higher than top surfaces of the isolation regions, wherein the semiconductor fin has a first lengthwise direction; and

a dielectric dummy fin protruding higher than the top surfaces of the isolation regions, wherein the dielectric dummy fin has a second lengthwise direction parallel to the first lengthwise direction, wherein the dielectric dummy fin has a top width and a bottom width greater than the top width, with the top width and the bottom width being measured in a widthwise direction perpendicular to the first lengthwise direction, and wherein the dielectric dummy fin has a first top surface lower than a second top surface of the semiconductor fin.

13. The device of claim 12 , wherein the dielectric dummy fin is tapered, and from a bottom end of the dielectric dummy fin to a top end of the dielectric dummy fin, widths of the dielectric dummy fin reduce continuously.

14. The device of claim 12 further comprising:

a gate stack extending on a top surface and sidewalls of the semiconductor fin; and

a gate isolation region over and contacting the dielectric dummy fin, wherein a first sidewall of the gate isolation region contacts a second sidewall of the gate stack.

15. The device of claim 14 , wherein the gate isolation region comprises:

a vertical-and-straight sidewall, and a slanted-and-straight bottom surface connecting to a bottom end of the vertical-and-straight sidewall, wherein the slanted-and-straight bottom surface has at least a portion lower than a top end of the dielectric dummy fin, and the gate isolation region contacts an additional sidewall of the dielectric dummy fin.

16. The device of claim 12 , wherein the dielectric dummy fin comprises a plurality of sub-layers, with outer sub-layers of the plurality of sub-layers having opposing portions on opposing sides of the respective inner sub-layers of the plurality of sub-layers, and wherein top surfaces of the outer sub-layers are lower than top surfaces of the respective inner sub-layers.

17. A device comprising:

a dielectric dummy fin;

a first protruding semiconductor fin and a second protruding semiconductor fin on opposing sides of the dielectric dummy fin, wherein a first top surface of the dielectric dummy fin is lower than second top surfaces of the first protruding semiconductor fin and the second protruding semiconductor fin;

a first gate stack on the first protruding semiconductor fin;

a second gate stack on the second protruding semiconductor fin; and

a gate isolation region between, and contacting, the first gate stack and the second gate stack, wherein the gate isolation region is over and contacting the dielectric dummy fin.

18. The device of claim 17 , wherein the dielectric dummy fin has a tapered profile, with upper widths of upper portions of the dielectric dummy fin being increasingly smaller than lower portions of the respective lower widths of the dielectric dummy fin.

19. The device of claim 18 further comprising:

isolation regions; and

a semiconductor strip between the isolation region, wherein the semiconductor strip is overlapped by the first protruding semiconductor fin, and wherein the semiconductor strip has an additional tapered profile, with upper widths of additional upper portions of the semiconductor strip being greater than lower widths of respective lower portions of the semiconductor strip.

20. The device of claim 12 , wherein the dielectric dummy fin is comprised in a dielectric strip, with the dielectric strip penetrating through the isolation regions, and wherein the dielectric strip forms vertical interfaces with the isolation regions.