Edge interface placements to enable chiplet rotation into multi-chiplet cluster

1. A system comprising:

a substrate including conductive interconnect;

multiple chiplets arranged on the substrate and interconnected using the conductive interconnect of the substrate;

wherein a chiplet includes multiple columns of multiple input-output (I/O) channels and the I/O channels are connected to a block of I/O pads and each side of the chiplet includes multiple blocks of the I/O pads including a first side of the chiplet and an adjacent side of the chiplet adjacent to the first side;

wherein the multiple blocks of I/O pads on the side of the chiplet are arranged symmetrically relative to a centerline of the chiplet and each block of I/O pads on the side of the chiplet is at a common distance from any adjacent block of I/O pads on the side; and

wherein the multiple blocks of I/O pads of the first side of the chiplet are each attached to a principal I/O channel, and the multiple blocks of I/O pads of the adjacent side are each attached to a subordinate I/O channel.

2. The system of claim 1 , wherein each block of I/O pads on the side of the chiplet is placed at a periphery of the chiplet at a distance from a centerline of the chiplet equal to one half of the distance between the multiple blocks of the I/O pads on a side.

3. The system of claim 1 , wherein each chiplet includes an even number of blocks of I/O pads on a side of the chiplet, and each of the blocks of I/O pads is placed at a periphery of the chiplet at a distance from a centerline of the chiplet equal to the one half of the distance between adjacent blocks of I/O pads.

4. The system of claim 1 , wherein each chiplet includes an odd number of blocks of I/O pads on a side of the chiplet, including a center block of I/O pads; and wherein the center block of I/O pads is centered on a center line of the chiplet and the other blocks of I/O pads are placed at the distance from the centerline of the chiplet equal to one half of the distance between the other blocks of I/O pads.

5. The system of claim 1 , wherein the multiple blocks of I/O pads are multiple blocks of micro-bumps on the chiplet.

6. The system of claim 1 , including:

a first chiplet having a first block of multiple I/O pads that includes a principal die-to-die physical layer interface including one or more pads to transmit a data transfer clock; and

a second chiplet having a second block of multiple I/O that includes a subordinate die-to-die physical layer interface including one or more pads to receive the data transfer clock, the second block of I/O pads connected to the first block of I/O pads by a die-to-die physical layer interconnect.

7. The system of claim 6 , including:

a third chiplet having a third block of multiple I/O pads that includes another principal die-to-die physical layer interface; and

wherein the first chiplet has a fourth block of multiple I/O pads that includes another subordinate die-to-die physical layer interface that is connected to the principal die-to-die physical layer interface of the third chiplet by the die-to-die physical layer interconnect.

8. The system of claim 1 , wherein the substrate includes an interposer included in a chip on wafer silicon substrate package.

9. The system of claim 1 , wherein the substrate includes an interposer that includes an embedded multi-die interconnect bridge (EMIB).

10. The system of claim 1 , wherein the substrate is an organic substrate.

11. The system of claim 1 , wherein the multiple chiplets arranged on the interposer include a memory controller chiplet and a memory device chiplet.

12. The system of claim 1 , wherein the interconnect of the interposer includes a chiplet mesh network.

13. A memory device including:

an interposer including conductive interconnect;

multiple chiplets arranged on the interposer and interconnected, the multiple chiplets including a memory controller chiplet, wherein the memory controller chiplet and another chiplet include a chiplet network interface (CPI);

wherein the memory controller chiplet includes multiple columns of multiple input-output (I/O) channels and the columns of the I/O channels are connected to I/O micro-bump blocks and each side of the chiplet includes multiple I/O micro-bump blocks including a first side of the chiplet and an adjacent side of the chiplet adjacent to the first side, wherein the multiple blocks of I/O pads of the first side of the chiplet are each attached to a principal I/O channel and the multiple blocks of I/O pads of the adjacent side are each attached to a subordinate I/O channel; and

wherein an I/O micro-bump block is placed at a periphery of the chiplet at a distance from a centerline of the chiplet equal to one half of the distance between I/O micro-bump blocks on a side of the chiplet.

14. The memory device of claim 13 ,

wherein a side of the memory controller chiplet includes an even number of advanced interface bus (AIB) channels connected to an even number of I/O micro-bump blocks, and the I/O micro-bump blocks are placed at the periphery of the memory controller chiplet at a distance from a centerline of the memory controller chiplet equal to the one half of the distance between adjacent I/O micro-bump blocks; and

wherein a facing side of the other chiplet includes an even number of AIB channels connected to an even number of I/O micro-bumps aligned with the micro-bump blocks of the memory controller chiplet.

15. The memory device of claim 13 ,

wherein a side of the memory controller chiplet includes an odd number of advanced interface bus (AIB) channels connected to an odd number of I/O micro-bump blocks including a center I/O micro-bump block, and the center I/O micro-bump block is centered on the center line of the memory controller chiplet and the other I/O micro-bump blocks are placed at are distance from the centerline of the chiplet equal to one half of the distance between the other I/O micro-bump blocks; and

wherein a facing side of the other chiplet includes an odd number of AIB channels connected to an odd number of I/O micro-bumps aligned with the I/O micro-bump blocks of the memory controller chiplet.