Source/drain contact spacers and methods of forming same
View Patent ↗Source/drain contact spacers for improving integrated circuit device performance and methods of forming such are disclosed herein. An exemplary method includes etching an interlayer dielectric (ILD) layer to form a source/drain contact opening that exposes a contact etch stop layer (CESL) disposed over a source/drain feature, depositing a source/drain contact spacer layer that partially fills the source/drain contact opening and covers the ILD layer and the exposed CESL, and etching the source/drain contact spacer layer and the CESL to extend the source/drain contact opening to expose the source/drain feature. The etching forms source/drain contact spacers. The method further includes forming a source/drain contact to the exposed source/drain feature in the extended source/drain contact opening. The source/drain contact is formed over the source/drain contact spacers and fills the extended source/drain contact opening. A silicide feature can be formed over the exposed source/drain feature before forming the source/drain contact.
1. An integrated circuit device comprising:
a gate structure disposed over a substrate;
a source/drain feature disposed adjacent to the gate structure;
a source/drain contact disposed over the source/drain feature, wherein the source/drain contact extends through an interlayer dielectric layer and a contact etch stop layer to the source/drain feature; and
a source/drain contact spacer disposed between sidewalls of the source/drain contact and the interlayer dielectric layer, wherein a portion of the contact etch stop layer is disposed between the source/drain contact spacer and the source/drain feature, such that the source/drain contact spacer does not physically contact the source/drain feature.
2. The integrated circuit device of claim 1 , wherein a material of the source/drain contact spacer is the same as a material of the contact etch stop layer.
3. The integrated circuit device of claim 1 , wherein a material of the source/drain contact spacer is different than a material of the contact etch stop layer.
4. The integrated circuit device of claim 1 , wherein the source/drain contact spacer is a silicon nitride layer.
5. The integrated circuit device of claim 1 , wherein the source/drain contact spacer is a silicon oxynitride layer.
6. The integrated circuit device of claim 1 , wherein the source/drain contact spacer extends partially through the contact etch stop layer.
7. The integrated circuit device of claim 1 , wherein a thickness of the source/drain contact spacer is tapered along the source/drain contact.
8. The integrated circuit device of claim 1 , further comprising a silicide feature disposed between the source/drain feature and the source/drain contact.
9. The integrated circuit device of claim 1 , wherein a thickness of the portion of the contact etch stop layer is less than or equal to about 10 nm.
10. An integrated circuit device comprising:
a first contact etch stop layer;
a first interlayer dielectric layer disposed over the first contact etch stop layer;
a second contact etch stop layer disposed over the first interlayer dielectric layer;
a second interlayer dielectric layer disposed over the second contact etch stop layer;
a source/drain contact that extends through the second interlayer dielectric layer, the second contact etch stop layer, the first interlayer dielectric layer, and the first contact etch stop layer and physically contacts a silicide feature, wherein the silicide feature is disposed between the source/drain contact and a source/drain; and
a source/drain contact dielectric liner layer disposed between sidewalls of the source/drain contact and the second interlayer dielectric layer, the second contact etch stop layer, the first interlayer dielectric layer, and the first contact etch stop layer, wherein the first contact etch stop layer is disposed between and separates the source/drain contact dielectric liner layer from a top surface of the source/drain.
11. The integrated circuit device of claim 10 , wherein the silicide feature includes titanium and silicon and the source/drain includes silicon and boron.
12. The integrated circuit device of claim 10 , wherein a top surface of the silicide feature is above a top surface of the source/drain and below a top surface of the first contact etch stop layer relative to a top surface of a substrate.
13. The integrated circuit device of claim 10 , wherein a thickness of the source/drain contact dielectric liner layer decreases from the second interlayer dielectric layer to the first contact etch stop layer.
14. The integrated circuit device of claim 10 , wherein a thickness of the source/drain contact dielectric liner layer increases from the second interlayer dielectric layer to the first contact etch stop layer.
15. The integrated circuit device of claim 10 , wherein a thickness of the source/drain contact dielectric liner layer is uniform from the second interlayer dielectric layer to the first contact etch stop layer.
16. An integrated circuit device comprising:
a first gate structure, a second gate structure, and an epitaxial source/drain disposed between the first gate structure and the second gate structure;
a first contact etch stop layer over first sidewalls of the first gate structure, second sidewalls of the second gate structure, and a top surface of the epitaxial source/drain;
a first interlayer dielectric layer disposed over the first contact etch stop layer and between the first gate structure and the second gate structure;
a second contact etch stop layer disposed over the first contact etch stop layer, the first interlayer dielectric layer, the first gate structure, and the second gate structure;
a second interlayer dielectric layer disposed over the second contact etch stop layer, the first interlayer dielectric layer, the first contact etch stop layer, the first gate structure, and the second gate structure;
a source/drain contact coupled to the epitaxial source/drain, wherein the source/drain contact extends through the second interlayer dielectric layer, the second contact etch stop layer, the first interlayer dielectric layer, and the first contact etch stop layer; and
a source/drain contact spacer disposed between sidewalls of the source/drain contact and the second interlayer dielectric layer, the second contact etch stop layer, and the first interlayer dielectric layer, wherein the first contact etch stop layer separates a bottom surface of the source/drain contact spacer from the top surface of the epitaxial source/drain.
17. The integrated circuit device of claim 16 , wherein the first interlayer dielectric layer is disposed between the first contact etch stop layer over the first sidewalls of the first gate structure and the source/drain contact spacer and between the first contact etch stop layer over the second sidewalls of the second gate structure and the source/drain contact spacer.
18. The integrated circuit device of claim 16 , wherein the first contact etch stop layer disposed over the top surface of the epitaxial source/drain has first portions having a first thickness and second portions having a second thickness, wherein the second thickness is less than the first thickness, and further wherein the second portions having the second thickness separate the bottom surface of the source/drain contact spacer from the top surface of the epitaxial source/drain.
19. The integrated circuit device of claim 16 , further comprising a silicide feature disposed between the source/drain contact and the epitaxial source/drain, wherein the first contact etch stop layer physically contacts the silicide feature.
20. The integrated circuit device of claim 19 , wherein a top surface of the silicide feature is above the top surface of the epitaxial source/drain.