Semiconductor device and inverter
In an embodiment, a semiconductor device is provided that includes a lateral transistor device having a source, a drain and a gate, and a monolithically integrated capacitor coupled between the gate and the drain.
1. A semiconductor device, comprising:
a lateral transistor device having a source, a drain and a gate; and
a monolithically integrated additional capacitor coupled between the gate and the drain and that is also coupled in parallel with the inherent gate drain capacitance C GD of the lateral transistor device,
wherein the semiconductor device has a reverse transfer capacitance C rss ,
wherein C rss(Vds=0V) /C rss(Vds=400V) <50,
wherein Vas is the drain-source voltage of the lateral transistor device,
wherein the additional capacitor has a capacitance C M that is greater than C GD .
2. The semiconductor device of claim 1 , further comprising:
a semiconductor body having a first surface, the lateral transistor device comprising a source finger electrode, a drain finger electrode and a gate finger electrode arranged on the first surface of the semiconductor body, the gate finger electrode being arranged laterally between the source finger electrode and the drain finger electrode; and
a metallization structure arranged on the first surface,
wherein the additional capacitor is integrated into the metallization structure and coupled between the gate finger electrode and the drain finger electrode.
3. The semiconductor device of claim 2 , wherein the additional capacitor is arranged on the first surface laterally adjacent the source finger electrode, the drain finger electrode and the gate finger electrode.
4. The semiconductor device of claim 2 , wherein the additional capacitor is formed on the first surface and comprises a first plate formed from a first conductive layer of the metallization structure, and a second plate formed from a second conductive layer of the metallization structure, and wherein the first plate and the second plate are spaced apart from one another by a first insulation layer of the metallization structure.
5. The semiconductor device of claim 4 , wherein:
the first plate of the additional capacitor extends from a gate runner formed from the first conductive layer, the gate runner being electrically coupled to the gate finger electrode, or the first plate extends from a gate pad formed from the first conductive layer, the gate pad being electrically coupled to the gate finger electrode; and
the second plate of the additional capacitor extends from a drain bus formed from the second conductive layer, the drain bus being electrically coupled to the drain finger electrode.
6. The semiconductor device of claim 2 , wherein the lateral transistor device further comprises an active area that contributes to current switching and the additional capacitor is positioned above the active area.
7. The semiconductor device of claim 6 , wherein the additional capacitor is arranged at least partially above the source finger electrode.
8. The semiconductor device of claim 7 , wherein:
the metallization structure further comprises a third conductive layer, the third conductive layer comprising a source finger arranged on the source finger electrode, a drain finger arranged on the drain finger electrode, and a gate runner positioned laterally adjacent the gate finger electrode, the source finger electrode and the drain finger electrode;
a first conductive layer of the metallization structure is arranged above the source finger and insulated from the source finger by a second insulation layer.
9. The semiconductor device of claim 8 , wherein:
a second conductive layer of the metallization structure comprises alternate drain and source buses that are arranged vertically above the source finger and the drain finger and extend substantially perpendicularly to the source finger and the drain finger;
the source finger is coupled to the source bus by a first conductive via extending through a first insulation layer; and
the drain finger is coupled to the drain bus by a second conductive via extending through the first insulation layer.
10. The semiconductor device of claim 9 , further comprising:
a third insulation layer positioned between the source finger and the drain finger of the third conductive layer; and
a fourth insulation layer arranged on the first surface that extends between the source finger electrode and the drain finger electrode and covers the gate finger electrode,
wherein the third insulation layer is arranged on the fourth insulation layer.
11. The semiconductor device of claim 10 , wherein the first conductive layer is coupled to the gate runner by a third conductive via that extends through the third and fourth insulation layers.
12. The semiconductor device of claim 1 , wherein the lateral transistor device is a III-V semiconductor transistor device.
13. The semiconductor device of claim 1 , wherein the lateral transistor device is a Group III nitride-based transistor device.
14. An inverter, comprising:
one or more half bridge circuits, each comprising a first switch coupled in series with a second switch,
wherein at least one of the first switch and the second switch comprises the semiconductor device of claim 1 .
15. The inverter of claim 14 , further comprising gate driver circuitry configured to actively control gate current of at least one of the first switch and the second switch.
16. The semiconductor device of claim 1 , wherein C M is at least 10 times larger than C GD .