Display panel

1. A display panel, comprising:

a substrate including a transmissive area, a first non-display area surrounding the transmissive area, and a display area at least partially surrounding the first non-display area;

a plurality of display elements placed in the display area, each of the plurality of display elements including a pixel electrode;

a plurality of scan lines arranged in the display area, at least one of the plurality of scan lines extending through the first non-display area and detouring along an edge of the transmissive area;

a connection line placed in the first non-display area and at least partially overlapping at least one of the plurality of scan lines in the first non-display area, the connection line being on a first layer which is a same layer as the pixel electrode;

a first line disposed on a second layer different from the first layer; and

a second line disposed on a third layer different from the first layer and at an opposite side with respect to the first line,

wherein the first line is connected to the connection line through a first contact hole, and the second line is connected to the connection line through a second contact hole,

wherein a width of the connection line where the at least one of the plurality of scan lines overlaps is greater than a width of either the first line or the second line.

2. The display panel as claimed in claim 1 , wherein the width of the connection line is greater than a width of each of the plurality of scan lines.

3. The display panel as claimed in claim 1 , wherein the first line is disposed on a same layer as the second line.

4. The display panel as claimed in claim 1 , further comprising:

a plurality of electrode voltage lines adjacent to the plurality of scan lines with an insulating layer therebetween and detouring along an edge of the transmissive area;

a driving thin film transistor in the display area, the driving thin film transistor including a driving gate electrode; and

a storage capacitor in the display area, the storage capacitor overlapping the driving thin film transistor,

wherein:

the plurality of scan lines are on a same layer as that of the driving gate electrode, and

the plurality of electrode voltage lines are on a same layer as that of a second storage capacitor plate of the storage capacitor.

5. The display panel as claimed in claim 4 , wherein the width of the connection line is greater than a width of each of the plurality of electrode voltage lines.

6. The display panel as claimed in claim 4 , wherein the connection line at least partially overlaps the plurality of electrode voltage lines.

7. The display panel as claimed in claim 4 , wherein the plurality of scan lines do not overlap the plurality of electrode voltage lines.

8. The display panel as claimed in claim 1 , wherein an interval between the plurality of scan lines arranged in the first non-display area is less than an interval between the plurality of scan lines arranged in the display area.

9. The display panel as claimed in claim 1 , further comprising a common power voltage wiring in the non-display area, the common power voltage wiring surrounding at least a portion of the display area and being configured to transfer a common voltage to the display area,

wherein the connection line is between the transmissive area and the common power voltage wiring.

10. A display panel, comprising:

a substrate including a transmissive area, a first non-display area surrounding the transmissive area, and a display area at least partially surrounding the first non-display area;

a plurality of display elements in the display area, each of the plurality of display elements including a pixel electrode;

a plurality of scan lines arranged in the display area, at least one of the plurality of scan lines extending through the first non-display area and detouring along an edge of the transmissive area;

a connection line in the first non-display area on a first layer;

a first line disposed on a second layer different from the first layer and connected to the connection line; and

a second line disposed on a third layer different from the first layer and connected to the connection line,

wherein the connection line at least partially overlaps the plurality of scan lines.

11. The display panel as claimed in claim 10 , wherein:

the plurality of scan lines each extend in a first direction and include a curved portion in the first non-display area, and

the connection line extends in the first direction and includes a straight line portion in the first non-display area.

12. The display panel as claimed in claim 10 , further comprising a plurality of electrode voltage lines adjacent to the plurality of scan lines with an insulating layer therebetween and detouring along an edge of the transmissive area.

13. The display panel as claimed in claim 12 , wherein the connection line at least partially overlaps the plurality of electrode voltage lines.

14. The display panel as claimed in claim 12 , wherein the plurality of scan lines do not overlap the plurality of electrode voltage lines.

15. The display panel as claimed in claim 10 , further comprising a common power voltage wiring in the non-display area, the common power voltage wiring surrounding at least a portion of the display area and being configured to transfer a common voltage to the display area,

wherein the connection line is between the transmissive area and the common power voltage wiring.

16. The display panel as claimed in claim 10 , wherein the connection line is disposed on a same layer as that of the pixel electrode.

17. The display panel as claimed in claim 1 , wherein

the first line is a first driving line connected to a first scan driving circuit, and

the second line is a second driving line connected to a second scan driving circuit.

18. The display panel as claimed in claim 10 , wherein

the first line is a first driving line connected to a first scan driving circuit, and

the second line is a second driving line connected to a second scan driving circuit.

19. A display panel, comprising:

a substrate including a transmissive area, a first non-display area surrounding the transmissive area, a display area at least partially surrounding the first non-display area, and a second non-display area surrounding the display area and the first non-display area;

a plurality of display elements placed in the display area, each of the plurality of display elements including a pixel electrode;

a plurality of scan lines arranged in the display area, at least one of the plurality of scan lines extending through the first non-display area and detouring along an edge of the transmissive area;

a connection line placed in the first non-display area and at least partially overlapping at least one of the plurality of scan lines in the first non-display area, the connection line being on a first layer which is a same layer as the pixel electrode;

a first scan circuit and a second scan circuit in the second non-display area;

a first driving line connected to the first scan circuit and extending along the second non-display area, the first driving line disposed on a second layer different from the first layer; and

a second driving line connected to the second scan circuit and extending along the second non-display area, the second driving line disposed on a third layer different from the first layer and at an opposite side with respect to the first driving line, wherein

the first driving line is connected to the connection line through a first contact hole,

the second driving line is connected to the connection line through a second contact hole, and

a width of the connection line where the at least one of the plurality of scan lines overlaps is greater than a width of either the first line or the second line.

20. The display panel as claimed in claim 19 , wherein the first scan circuit and the second scan circuit are configured to provide scan signals.