IP Library › Granted Patent US 11,166,032
Granted Patent B2
US 11,166,032 · App. 17/080,141 · Granted Nov 2, 2021

Encoder, decoder, encoding method, and decoding method

Inventors: Alec Hodgkinson (Pescadero, CA); Luca Rigazio (Campbell, CA); Takahiro Nishi (Nara, JP); Kiyofumi Abe (Osaka, JP); Ryuichi Kanoh (Osaka, JP); Tadamasa Toma (Osaka, JP)
Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
H04N19/184G06N3/08H04N19/124H04N19/136H04N19/46H04N19/85
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Quick Facts
Patent No.
US 11,166,032
App. No.
17/080,141
Granted
Nov 2, 2021
Kind
B2
Abstract

An encoder includes circuitry and memory. Using the memory, the circuitry: encodes an original image and decodes the original image encoded, to generate a first bitstream and a local decoded image; encodes supplemental information and decodes the encoded supplemental information, to generate a second bitstream and local decoded supplemental information; inputs data based on the local decoded image and the local decoded supplemental information to a post processing network which is a neural network, to cause a reconstructed image to be output from the post processing network, the reconstructed image corresponding to the original image and being to be used to encode a following original image which follows the original image; and concatenates the first bitstream and the second bitstream to generate a concatenated bitstream.

Claims (72)

1. An encoder, comprising:

circuitry; and

memory,

wherein, using the memory, the circuitry:

encodes an original image and decodes the original image encoded, to generate a first bitstream and a local decoded image;

encodes supplemental information and decodes the encoded supplemental information, to generate a second bitstream and local decoded supplemental information;

inputs data based on the local decoded image and the local decoded supplemental information to a post processing network which is a neural network, to cause a reconstructed image to be output from the post processing network, the reconstructed image corresponding to the original image and being to be used to encode a following original image which follows the original image; and

concatenates the first bitstream and the second bitstream to generate a concatenated bitstream.

2. The encoder according to claim 1 ,

wherein, when causing the reconstructed image to be output, the circuitry

separately inputs the local decoded image and the local decoded supplemental information as the data to the post processing network, to cause the reconstructed image to be output from the post processing network.

3. The encoder according to claim 1 ,

wherein the circuitry:

adds the local decoded image and the local decoded supplemental information; and

when causing the reconstructed image to be generated,

inputs a result of adding the local decoded image and the local decoded supplemental information as the data to the post processing network, to cause the reconstructed image to be output from the post processing network.

4. The encoder according to claim 1 ,

wherein the circuitry

subtracts the local decoded image from the original image to generate the supplemental information as a residual image.

5. The encoder according to claim 1 ,

wherein when encoding the supplemental information, the circuitry downsamples the supplemental information.

6. The encoder according to claim 5 ,

wherein when decoding the encoded supplemental information, the circuitry

upsamples the downsampled supplemental information.

7. The encoder according to claim 1 ,

wherein when encoding the supplemental information, the circuitry

inputs the supplemental information to an encoder network which is a neural network, to cause the encoded supplemental information to be output from the encoder network.

8. The encoder according to claim 7 ,

wherein, when decoding the encoded supplemental information, the circuitry

inputs the encoded supplemental information to a decoder network which is a neural network, to cause the decoded encoded supplemental information to be output from the decoder network.

9. The encoder according to claim 1 ,

wherein, when encoding the supplemental information, the circuitry

quantizes the supplemental information.

10. The encoder according to claim 1 ,

wherein, when encoding the supplemental information, the circuitry

entropy encodes the supplemental information.

11. A decoder, comprising:

circuitry; and

memory,

wherein, using the memory, the circuitry:

decodes a first bitstream included in a concatenated bitstream to generate a decoded image of codec;

decodes a second bitstream included in the concatenated bitstream to generate decoded supplemental information; and

inputs data based on the decoded image of codec and the decoded supplemental information to a post processing network which is a neural network, to cause a decoded image to be output from the post processing network.

12. The decoder according to claim 11 ,

wherein, when causing the decoded image to be output, the circuitry

separately inputs the decoded image of codec and the decoded supplemental information as the data to the post processing network, to cause the decoded image to be output from the post processing network.

13. The decoder according to claim 11 ,

wherein the circuitry:

adds the decoded image of codec and the decoded supplemental information; and

when causing the decoded image to be output,

inputs a result of adding the decoded image of codec and the decoded supplemental information as the data to the post processing network, to cause the decoded image to be output from the post processing network.

14. The decoder according to claim 11 ,

wherein, when decoding the second bitstream, the circuitry

upsamples downsampled supplemental information which is obtained from the second bitstream, to generate the decoded supplemental information.

15. The decoder according to claim 11 ,

wherein, when decoding the second bitstream, the circuitry

inputs encoded supplemental information which is obtained from the second bitstream to a decoder network which is a neural network, to cause the decoded supplemental information to be output from the decoder network.

16. The decoder according to claim 11 ,

wherein, when decoding the second bitstream, the circuitry

entropy decodes the second bitstream.

17. The decoder according to claim 11 ,

wherein, when decoding the second bitstream, the circuitry

inverse quantizes the second bitstream.

18. An encoding method, comprising:

encoding a current original image and decoding the current original image encoded, to generate a first bitstream and a local decoded image;

encoding supplemental information and decoding the encoded supplemental information, to generate a second bitstream and local decoded supplemental information;

inputting data based on the local decoded image and the local decoded supplemental information to a post processing network which is a neural network, to cause a reconstructed image to be output from the post processing network, the reconstructed image corresponding to the original image and being to be used to encode a following original image which follows the original image; and

concatenating the first bitstream and the second bitstream to generate a concatenated bitstream.

19. A decoding method, comprising:

decoding a first bitstream included in a concatenated bitstream to generate a decoded image of codec;

decoding a second bitstream included in the concatenated bitstream to generate decoded supplemental information; and

inputting data based on the decoded image of codec and the decoded supplemental information to a post processing network which is a neural network, to cause a decoded image to be output from the post processing network.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 2, 2021
From: HODGKINSON, ALEC; RIGAZIO, LUCA; NISHI, TAKAHIRO; ABE, KIYOFUMI; KANOH, RYUICHI; TOMA, TADAMASA
To: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
Reel/Frame 056740/0418 →
Continuity (3)
Continuation PCTJP2019017553 · Apr 25, 2019
Provisional Application 62663451 · Apr 27, 2018
Related Publication 20210044811A1 · Feb 11, 2021