Tunnel drift step recovery diode
Devices, methods and techniques are disclosed for providing a multi-layer diode without voids between layers. In one example aspect, a multi-stack diode includes at least two Drift Step Recovery Diodes (DSRDs). Each DSRD comprises a first layer having a first type of dopant, a second layer forming a region with at least ten times lower concentration of dopants compared to the adjacent layers, and a third layer having a second type of dopant that is opposite to the first type of dopant. The first layer of a second DSRD is positioned on top of the third layer of first DSRD. The first layer of the second DSRD and the third layer of the first DSRD are degenerate to form a tunneling diode at an interface of the first DSRD and second DSRD, the tunneling diode demonstrating a linear current-voltage characteristic.
1. A multi-stack diode comprising at least two drift step recovery diodes (DSRDs), each DSRD comprising:
a first layer having a first type of dopant,
a second layer forming a region with at least ten times lower concentration of dopants compared to adjacent layers thereto, and
a third layer having a second type of dopant that is opposite to the first type of dopant,
wherein the first layer of a second DSRD is positioned on top of the third layer of a first DSRD, and wherein the first layer of the second DSRD and the third layer of the first DSRD are degenerate to form a tunneling diode at an interface of the first DSRD and the second DSRD, the tunneling diode demonstrating a linear current-voltage characteristic.
2. The multi-stack diode of claim 1 , wherein the first layer of the second DSRD comprises a degenerate P-type region and the third layer of the first DSRD comprises a degenerate N-type region.
3. The multi-stack diode of claim 2 , wherein the third layer of the second DSRD comprises a N-type region and the first layer of the first DSRD comprises a P-type region.
4. The multi-stack diode of claim 1 , wherein the first layer of the second DSRD comprises a degenerate N-type region and the third layer of the first DSRD comprises a degenerate P-type region.
5. The multi-stack diode of claim 4 , wherein the third layer of the second DSRD comprises a P-type region and the first layer of the first DSRD comprises a N-type region.
6. The multi-stack diode of claim 1 , wherein the tunneling diode is doped at a doping concentration in a range of 1×10 18 cm −3 to 1×10 20 cm −3 .
7. The multi-stack diode of claim 1 , wherein the tunneling diode is doped at a doping concentration higher than 5×10 19 cm −3 .
8. The multi-stack diode of claim 1 , wherein the tunneling diode has a reverse breakdown voltage equal to or lower than 200 meV.
9. The multi-stack diode of claim 1 , wherein each of the at least two DSRDs is operable to turn on at a voltage between 650 meV to 750 meV, and wherein the tunneling diode is operable to break down at a voltage between 180 meV to 250 meV.
10. A method for producing a multi-stack diode, comprising:
determining a number of Drift Step Recovery Diodes (DSRDs) in the multi-stack diode,
growing, for each DSRD:
a first layer having a first type of dopant,
a second layer forming a region with at least ten times lower concentration of dopants compared to adjacent layers thereto, and
a third layer having a second type of dopant that is opposite to the first type of dopant; and
repeating the growing until the number of DSRDs are completed, wherein the third layer of a first DSRD and the first layer of an adjacent, second DSRD are degenerate to form a tunneling diode at an interface of the first DSRD and the second DSRD, the tunneling diode demonstrating a linear current-voltage characteristic.
11. The method of claim 10 , wherein the first layer of the second DSRD comprises a degenerate P-type region and the third layer of the first DSRD comprises a degenerate N-type region.
12. The method of claim 11 , wherein the third layer of the second DSRD comprises a N-type region and the first layer of the first DSRD comprises a P-type region.
13. The method of claim 10 , wherein the first layer of the second DSRD comprises a degenerate N-type region and the third layer of the first DSRD comprises a degenerate P-type region.
14. The method of claim 12 , wherein the third layer of the second DSRD comprises a P-type region and the first layer of the first DSRD comprises a N-type region.
15. The method of claim 10 , wherein the growing is performed by epitaxial growth.
16. The method of claim 10 , further comprising:
adjusting a doping concentration of the third layer of the first DSRD and a doping concentration of the first layer of the second DSRD from a first concentration level to a second concentration level.
17. The method of claim 16 , wherein adjusting the doping concentration comprises adjusting the doping concentration of the third layer of the first DSRD and the doping concentration of the first layer of the second DSRD to gradually approach the second concentration level that is substantially equal to a doping concentration level of the second layer.
18. The method of claim 10 , wherein the tunneling diode is doped at a doping concentration of at least 1×10 18 cm −3 .
19. The method of claim 10 , wherein the tunneling diode has a reverse breakdown voltage equal to or lower than 200 meV.
20. The method of claim 10 , comprising:
introducing one or more defects to the tunneling diode to allow a current to flow through the tunneling diode regardless of a bias polarity.