Receiver synchronization

1. A method, comprising:

responsive to an error signal being below a threshold value, storing a state value of a feedback loop;

transitioning a device within the feedback loop to a lower power state;

detecting a wake-up event;

responsive to the detected wake-up event, loading a previously stored feedback loop state value; and

enabling the feedback loop.

2. The method of claim 1 , wherein the device is a loop filter, and wherein storing the feedback loop state value comprises storing a value indicative of a frequency error.

3. The method of claim 1 , wherein the device is a decision feedback equalizer, and wherein storing the feedback loop state value comprises storing a value indicative of an equalizer coefficient.

4. The method of claim 1 , wherein the error signal comprises a mean square error value.

5. The method of claim 1 , further comprising adjusting the threshold value based on a value indicative of a cable length.

6. The method of claim 5 , wherein the value indicative of the cable length includes a gain value.

7. The method of claim 6 , wherein adjusting the threshold value comprises increasing the threshold value in response to an increase in the gain value.

8. The method of claim 1 , further comprising:

responsive to an error value being above a threshold value, determining a timing error value without decision feedback equalization; and

responsive to the error value being below the threshold value, determining the timing error value with the decision feedback equalization.

9. The method of claim 1 , wherein the feedback loop includes a timing error detector (TED), and the method further comprises:

before the TED achieves a lock state, determining a timing error value by the TED based on post-cursor inter-symbol interference but not pre-cursor inter-symbol interference; and

after the TED achieves the lock state, determining the timing error value by the TED based on both the post-cursor inter-symbol interference and the pre-cursor inter-symbol interference.

10. A receiver circuit, comprising:

a feedback loop;

a device comprising a register wherein the device is included in the feedback loop; and

a sequencer coupled to the feedback loop, the sequencer configured to:

responsive to an error signal being below a threshold value, cause the register to store a value indicative of the state of the feedback loop;

cause the feedback loop to transition to a lower power state;

responsive to a detected wake-up event, cause the previously stored value indicative of the state of the feedback loop to be loaded from the register into the device; and

enable the feedback loop.

11. The receiver circuit of claim 10 , wherein the device is a loop filter, wherein the feedback loop is a timing loop and wherein the value indicative of the state of the timing loop is a value indicative of a frequency error.

12. The receiver circuit of claim 10 , wherein the device is a decision feedback equalizer (DFE), wherein the feedback loop is a DFE loop and wherein the value indicative of the state of the DFE loop is a value indicative of equalizer coefficients.

13. The receiver circuit of claim 10 , wherein the error signal comprises a mean square error value.

14. The receiver circuit of claim 10 , wherein the sequencer is configured to adjust the threshold value based on a value indicative of a cable length.

15. The receiver circuit of claim 14 , further including an automatic gain control circuit, and wherein the value indicative of the cable length includes a gain value programmed into the automatic gain control circuit.

16. The receiver circuit of claim 15 , wherein the sequencer is configured to increase the threshold value in response to an increase in the gain value.

17. The receiver circuit of claim 10 , wherein the feedback loop is a timing loop and wherein the sequencer is configured to:

before the timing loop within the receiver circuit achieves a lock state, configure the timing loop to determine a timing error value without decision feedback equalization; and

responsive to the timing loop achieving the lock state, configure the timing loop to determine the timing error value with the decision feedback equalization.

18. The receiver circuit of claim 10 , wherein the feedback loop is a timing loop wherein the timing loop further includes a timing error detector (TED) coupled to the sequencer, and the sequencer is further configured to cause:

before the TED achieves a lock state, the TED to determine a timing error value based on post-cursor inter-symbol interference but not pre-cursor inter-symbol interference; and

after the TED achieves the lock state, the TED to determine the timing error value based on both the post-cursor inter-symbol interference and the pre-cursor inter-symbol interference.

19. A receiver circuit, comprising:

a feedback loop;

a device comprising a register wherein the device is included in the feedback loop; and

a sequencer coupled to the feedback loop, the sequencer configured to:

adjust a threshold value based on a value indicative of a cable length;

responsive to an error signal being below the threshold value, cause the register to store a value indicative of the state of the feedback loop;

cause the feedback loop to transition to a lower power state;

responsive to a detected wake-up event, cause the previously stored value indicative of the state of the feedback loop to be loaded from the register into the device; and

enable the feedback loop.

20. The receiver circuit of claim 19 , wherein the device is a loop filter, wherein the feedback loop is a timing loop and wherein the value indicative of the state of the timing loop is a value indicative of a frequency error.

21. The receiver circuit of claim 19 , wherein the device is a decision feedback equalizer (DFE), wherein the feedback loop is a DFE loop and wherein the value indicative of the state of the DFE loop is a value indicative of equalizer coefficients.

22. The receiver circuit of claim 19 , wherein the error signal comprises a mean square error value.