Delay-based side-channel analysis for trojan detection
View Patent ↗The present disclosure describes various embodiments of systems, apparatuses, and methods for detecting a Trojan inserted integrated circuit design using delay-based side channel analysis. In one such embodiment, an automated test generation algorithm produces test patterns that are likely to activate trigger conditions and change critical paths of an integrated circuit design.
1. A method of detecting a Trojan inserted integrated circuit design comprising:
applying test patterns as inputs to a golden integrated circuit device, wherein the test patterns are ordered to maximize a delay deviation between the golden integrated circuit device and the Trojan inserted integrated circuit design;
measuring a propagation delay of a critical path within the golden integrated circuit device;
applying the test patterns as inputs to a test integrated circuit device;
measuring a propagation delay of a critical path of the test integrated circuit device;
comparing the propagation delay of the test integrated circuit device with the propagation delay of the golden integrated circuit device; and
determining the test integrated circuit device to be a Trojan inserted integrated circuit device when the propagation delay of the test integrated circuit device exceeds the propagation delay of the golden integrated circuit device by a threshold value.
2. The method of claim 1 , wherein the test patterns activate a triggering condition of a Trojan circuit that is present in the test integrated circuit device and is not present in the golden integrated circuit device.
3. The method of claim 2 , wherein the critical path of the test integrated circuit device is different from the critical path of the golden integrated circuit device responsive to application of the test patterns as inputs, wherein the propagation delay of the test integrated circuit device exceeds the propagation delay of the golden integrated circuit device by a threshold value.
4. The method of claim 1 , further comprising determining the test integrated circuit device to not be a Trojan inserted integrated circuit device when the propagation delay of the test integrated circuit device does not exceed the propagation delay of the golden integrated circuit device by the threshold value.
5. The method of claim 1 , wherein the test patterns are generated using a Boolean satisfiability (SAT)-based approach.
6. The method of claim 1 , wherein a Hamming-distance based reordering of the test patterns is performed.
7. An apparatus for detecting a Trojan inserted integrated circuit design comprising:
a computer having memory and a processor that is configured to:
receive an output signal from an integrated circuit device;
apply test patterns as inputs to a golden integrated circuit device, wherein the test patterns are ordered to maximize a delay deviation between the golden integrated circuit device and the Trojan inserted integrated circuit design;
receive an output signal from the golden integrated circuit device in response to the applied test patterns;
measure a propagation delay of a critical path within the golden integrated circuit device;
store the propagation delay for the golden integrated circuit device in a data store;
apply the test patterns as inputs to a test integrated circuit device;
receive an output signal from the test integrated circuit device in response to the applied test patterns;
measure a propagation delay of a critical path of the test integrated circuit device;
compare the propagation delay of the test integrated circuit device with the propagation delay of the golden integrated circuit device from the data store; and
determine the test integrated circuit device to be a Trojan inserted integrated circuit device when the propagation delay of the test integrated circuit device exceeds the propagation delay of the golden integrated circuit device by a threshold value.
8. The apparatus of claim 7 , wherein the test patterns activate a triggering condition of a Trojan circuit that is present in the test integrated circuit device and is not present in the golden integrated circuit device.
9. The apparatus of claim 8 , wherein the critical path of the test integrated circuit device is different from the critical path of the golden integrated circuit device responsive to application of the test patterns as inputs, wherein the propagation delay of the test integrated circuit device exceeds the propagation delay of the golden integrated circuit device by a threshold value.
10. The apparatus of claim 7 , wherein the computer having the memory and the processor is further configured to determine the test integrated circuit device to not be a Trojan inserted integrated circuit device when the propagation delay of the test integrated circuit device does not exceed the propagation delay of the golden integrated circuit device by the threshold value.
11. The apparatus of claim 7 , wherein the test patterns are generated using a Boolean satisfiability (SAT)-based approach.
12. The apparatus of claim 7 , wherein a Hamming-distance based reordering of the test patterns is performed.
13. A non-transitory computer readable storage medium having instructions stored thereon that, in response to execution by a computing device, cause the computing device to perform operations comprising:
applying test patterns as inputs to a golden integrated circuit device, wherein the test patterns are ordered to maximize a delay deviation between the golden integrated circuit device and a Trojan inserted integrated circuit design;
measuring a propagation delay of a critical path within the golden integrated circuit device;
applying the test patterns as inputs to a test integrated circuit device;
measuring a propagation delay of a critical path of the test integrated circuit device;
comparing the propagation delay of the test integrated circuit device with the propagation delay of the golden integrated circuit device; and
determining the test integrated circuit device to be a Trojan inserted integrated circuit device when the propagation delay of the test integrated circuit device exceeds the propagation delay of the golden integrated circuit device by a threshold value.
14. The non-transitory computer readable storage medium of claim 13 , wherein the test patterns activate a triggering condition of a Trojan circuit that is present in the test integrated circuit device and is not present in the golden integrated circuit device.
15. The non-transitory computer readable storage medium of claim 13 , wherein the operations further comprise determining the test integrated circuit device to not be a Trojan inserted integrated circuit device when the propagation delay of the test integrated circuit device does not exceed the propagation delay of the golden integrated circuit device by the threshold value.
16. A method of detecting a Trojan inserted integrated circuit design comprising:
applying test patterns as inputs to a golden integrated circuit device;
measuring a propagation delay of a critical path within the golden integrated circuit device;
applying the test patterns as inputs to a test integrated circuit device;
measuring a propagation delay of a critical path of the test integrated circuit device;
comparing the propagation delay of the test integrated circuit device with the propagation delay of the golden integrated circuit device; and
determining the test integrated circuit device to be a Trojan inserted integrated circuit device when the propagation delay of the test integrated circuit device exceeds the propagation delay of the golden integrated circuit device by a threshold value,
wherein the test patterns activate a plurality of rare nodes within the golden integrated circuit device and the test integrated circuit device.
17. An apparatus for detecting a Trojan inserted integrated circuit design comprising:
a computer having memory and a processor that is configured to:
receive an output signal from an integrated circuit device;
apply test patterns as inputs to a golden integrated circuit device;
receive an output signal from the golden integrated circuit device in response to the applied test patterns;
measure a propagation delay of a critical path within the golden integrated circuit device;
store the propagation delay for the golden integrated circuit device in a data store;
apply the test patterns as inputs to a test integrated circuit device;
receive an output signal from the test integrated circuit device in response to the applied test patterns;
measure a propagation delay of a critical path of the test integrated circuit device;
compare the propagation delay of the test integrated circuit device with the propagation delay of the golden integrated circuit device from the data store; and
determine the test integrated circuit device to be a Trojan inserted integrated circuit device when the propagation delay of the test integrated circuit device exceeds the propagation delay of the golden integrated circuit device by a threshold value,
wherein the test patterns are configured to activate a plurality of rare nodes within the golden integrated circuit device and the test integrated circuit device.