Method and system for estimating junction temperature of power semiconductor device of power module

1. A method for estimating a junction temperature of a power semiconductor device of a power module and controlling the power module, the power module including a first power semiconductor device disposed adjacent to a heat sink for cooling and having a temperature sensor, and a second power semiconductor device disposed adjacent to the first power semiconductor device and having no temperature sensor, and the method comprising:

computing, by the processor, a junction temperature prediction value of the first power semiconductor device based on a power loss and a thermal resistance of the first power semiconductor device;

computing, by the processor, a junction temperature prediction value of the second power semiconductor device based on a power loss and a thermal resistance of the second power semiconductor device;

computing, by the processor, a temperature prediction value of the heat sink by subtracting the junction temperature prediction value of the first power semiconductor device from a sensing temperature sensed by the temperature sensor;

determining, by the processor, the junction temperature of the second power semiconductor device by adding the temperature prediction value of the heat sink to the junction temperature prediction value of the second power semiconductor device; and

stopping, by the processor, an operation of the power module in response to determining that the determined junction temperature of the second power semiconductor device is greater than a preset reference value.

2. The method according to claim 1 , wherein the computing of the junction temperature prediction value of the first power semiconductor device includes:

calculating, by the processor, the power loss of the first power semiconductor device; and

computing, by the processor, the junction temperature prediction value of the first power semiconductor device by multiplying the power loss of the first power semiconductor device by the thermal resistance of the first power semiconductor device.

3. The method according to claim 2 , wherein the calculating of the power loss of the first power semiconductor device includes calculating the power loss of the first power semiconductor device using a predetermined power loss computational formula using a plurality of parameters related to the operation of the power module as variables.

4. The method according to claim 2 , wherein the thermal resistance of the first power semiconductor device is determined based on a flow rate of coolant flowing through the heat sink.

5. The method according to claim 1 , wherein the computing of the junction temperature prediction value of the second power semiconductor device includes:

calculating, by the processor, the power loss of the second power semiconductor device; and

computing, by the processor, the junction temperature prediction value of the second power semiconductor device by multiplying the power loss of the second power semiconductor device by the thermal resistance of the second power semiconductor device.

6. The method according to claim 5 , wherein the calculating of the power loss of the second power semiconductor device includes calculating the power loss of the second power semiconductor device using a predetermined power loss computational formula using a plurality of parameters related to the operation of the power module as variables.

7. The method according to claim 5 , wherein the thermal resistance of the second power semiconductor device is determined based on a flow rate of coolant flowing through the heat sink.

8. The method according to claim 1 , wherein the first power semiconductor device is an insulated gate bipolar transistor (IGBT), and the second power semiconductor device is a diode.

9. A system for estimating a junction temperature of a power semiconductor device of a power module and controlling the power module, the power module including a first power semiconductor device disposed adjacent to a heat sink for cooling and having a temperature sensor, and a second power semiconductor device disposed adjacent to the first power semiconductor device and having no temperature sensor, and the system comprising:

a memory configured to store a predetermined power loss computational formula of each of the first and second power semiconductor devices using a plurality of parameters as variables and a thermal resistance of each of the first and second power semiconductor devices; and

a processor configured to determine a junction temperature of the second power semiconductor device based on information stored in the memory and a sensing temperature of the temperature sensor,

wherein the processor is configured to:

receive the plurality of parameters related to an operation of the power module to calculate the power loss of the first power semiconductor device, and compute a junction temperature prediction value of the first power semiconductor device based on the power loss and the thermal resistance of the first power semiconductor device,

receive the plurality of parameters related to the operation of the power module to calculate the power loss of the second power semiconductor device, and compute a junction temperature prediction value of the second power semiconductor device based on the power loss and the thermal resistance of the first power semiconductor device,

compute a temperature prediction value of the heat sink by subtracting the junction temperature prediction value of the first power semiconductor device from the sensing temperature sensed by the temperature sensor provided in the first power semiconductor device,

determine the junction temperature of the second power semiconductor device by adding the temperature prediction value of the heat sink to the junction temperature prediction value of the second power semiconductor device; and

stop an operation of the power module in response to determining that the determined junction temperature of the second power semiconductor device is greater than a preset reference value.

10. The system for estimating the junction temperature of the power semiconductor device of the power module according to claim 9 , wherein the memory is configured to store the preset reference value for a comparison with the second power semiconductor device.

11. The system for estimating the junction temperature of the power semiconductor device of the power module according to claim 9 , wherein the first power semiconductor device is an insulated gate bipolar transistor (IGBT), and the second power semiconductor device is a diode.