System and method for sub-column parallel digitizers for hybrid stacked image sensor using vertical interconnects
Embodiments of a hybrid imaging sensor and methods for pixel sub-column data read from the within a pixel array.
1. An imaging sensor comprising:
a pixel array comprising a plurality of pixel columns disposed on a first substrate, wherein each of the plurality of pixel columns is divided into a plurality of pixel sub-columns;
a plurality of supporting circuits disposed on one or more additional substrates, the plurality of supporting circuits comprising a plurality of circuit columns, wherein each of the plurality of circuit columns is divided into a plurality of circuit sub-columns; and
a plurality of interconnects for electrically connecting each pixel sub-column to one of the plurality of circuit sub-columns;
wherein each of the plurality of circuit sub-columns has an area, a size, and an aspect ratio, and each of the plurality of pixel sub-columns that corresponds to each one of the circuit sub-columns has an area, a size, and an aspect ratio; and
wherein the aspect ratio of at least one of the circuit sub-columns has a width equal to “N” times the width of the aspect ratio of one of said pixel sub-columns and a length equal to 1/“N” times the length of the aspect ratio of one of said pixel sub-columns.
2. The imaging sensor of claim 1 , wherein the one or more additional substrates are disposed remotely relative to the first substrate.
3. The imaging sensor of claim 1 , further comprising a pixel sub-column bus for each of the plurality of pixel sub-columns on the first substrate and a circuit sub-column bus for each of the plurality of circuit sub-columns on the one or more additional substrates.
4. The imaging sensor of claim 3 , wherein each pixel sub-column bus on the first substrate is at least partially superimposed relative to a corresponding circuit sub-column bus on the one or more additional substrates, wherein the first substrate and the one or more additional substrates are in a stacked configuration.
5. The imaging sensor of claim 4 , wherein at least one interconnect of the plurality of interconnects electrically connects each pixel sub-column to one of the plurality of circuit sub-columns by connecting the pixel sub-column bus for each of the plurality of pixel sub-columns on the first substrate with a corresponding circuit sub-column bus for each of the plurality of circuit sub-columns on the one or more additional substrates.
6. The imaging sensor of claim 3 , wherein electrical communication between the pixel sub-column bus and a corresponding circuit sub-column bus is provided by the interconnect such that each of the pixel sub-columns is read independently.
7. The imaging sensor of claim 1 , wherein each pixel sub-column is electronically isolated from other pixel sub-columns.
8. The imaging sensor of claim 1 , wherein each circuit sub-column is dedicated to one of the plurality of pixel sub-columns of the pixel array.
9. The imaging sensor of claim 1 , wherein the plurality of supporting circuits in each of the circuit sub-columns are configured to independently read and process data from a corresponding pixel sub-column, and wherein pixel sub-columns within a same pixel column are read simultaneously as part of a rolling shutter.
10. The imaging sensor of claim 1 , wherein the area of one of said pixel sub-columns is substantially equal to the area of one of said corresponding circuit sub-columns.
11. The imaging sensor of claim 1 , wherein the size of one of said pixel sub-columns is substantially equal to the size of one of said corresponding circuit sub-columns.
12. The imaging sensor of claim 1 , wherein the area of one of said pixel sub-columns is different than the area of one of said corresponding circuit sub-columns.
13. The imaging sensor of claim 1 , wherein the size of one of said pixel sub-columns is different to the size of one of said corresponding circuit sub-columns.
14. The imaging sensor of claim 1 , wherein the aspect ratio of one of said pixel sub-columns is substantially similar to the aspect ratio of one of said corresponding circuit sub-columns.
15. The imaging sensor of claim 1 , wherein the aspect ratio of one of said pixel sub-columns is different from the aspect ratio of one of said corresponding circuit sub-columns.
16. The imaging sensor of claim 1 , wherein each of the plurality of interconnects is positioned at a distance that is at least two pixel widths away from any other interconnects of the plurality of interconnects.
17. The imaging sensor of claim 1 , wherein said plurality of interconnects are spaced relative to one another at a distance that is greater than a pixel pitch of said pixel array.