Multi-chip package with extended frame
According to the various aspects, a multi-chip semiconductor package includes a package substrate, an interconnect frame extending beyond a first side edge of the package substrate, the interconnect frame including a bottom surface positioned over and coupled to a top surface of the package substrate, a first semiconductor device positioned at least partially over and coupled to the interconnect frame, and a second semiconductor device positioned on the bottom surface of the interconnect frame alongside of the package substrate. The interconnect frame further includes a redistribution layer and a frame construct layer, and a plurality of vias coupled to the redistribution layer, with the frame construct layer further includes a recessed area, and the first semiconductor device is positioned in the recessed area.
1. A device comprising:
a package substrate;
an interconnect frame extending beyond a first side edge of the package substrate, the interconnect frame comprising a bottom surface positioned over and coupled to a top surface of the package substrate;
a first semiconductor device positioned at least partially over and coupled to the interconnect frame; and
a second semiconductor device positioned on the bottom surface of the interconnect frame alongside of the package substrate;
wherein the interconnect frame further comprises a redistribution layer and a frame construct layer;
further comprising a plurality of vias coupled to the redistribution layer, wherein the first device is coupled to the plurality of vias for connection to the redistribution layer and second semiconductor is coupled to the redistribution layer through a plurality of solder bumps;
wherein the frame construct layer further comprises a recessed area, wherein some of the plurality of vias are positioned in the recess; and the first semiconductor device is positioned in the recessed area and coupled to the vias in the recessed area.
2. The device of claim 1 , further comprising a portion of the recessed area and a portion of the first semiconductor device extending beyond the at least one side edge of the package substrate.
3. The device of claim 2 , wherein the portion of the first semiconductor device extending beyond the at least one side edge of the package substrate is positioned over the second semiconductor device.
4. The device of claim 1 , further comprising the interconnect frame forming an extension platform for the package substrate extending beyond at least a second side edge of the package substrate and the recessed area comprises a cavity exposing the top surface of the package substrate.
5. The device of claim 1 , wherein the frame construct layer further comprises an embedded passive device.
6. The device of claim 5 , wherein the first semiconductor device is positioned at least partially over the cavity, further comprising a plurality of solder bumps positioned in the cavity coupling the first semiconductor device to the top surface of the package substrate.
7. The device of claim 6 , further comprising one or more additional recess semiconductor devices positioned in the recess and at least partially over the cavity, wherein the plurality of solder bumps couples the first semiconductor device and the one or more additional semiconductor devices to the top surface of the package substrate.
8. The device of claim 5 , further comprising one or more additional frame semiconductor devices coupled to the bottom surface of the interconnect frame alongside of the package substrate.
9. The device of claim 5 , further comprising an interposer coupled to the bottom surface of the interconnect frame alongside of the package substrate.
10. The device of claim 1 , wherein the frame construct layer further comprises an integrated heat spreader.
11. The device of claim 1 , wherein the frame construct layer further comprises an integrated electromagnetic shield.
12. A computing device comprising:
a printed circuit board;
a package substrate coupled to the printed circuit board, the package substrate comprising:
an interconnect frame extending beyond at least one side edge of the package substrate, the interconnect frame comprising a bottom surface positioned over and coupled to a top surface of the package substrate;
a first semiconductor device positioned at least partially over and coupled to the interconnect frame; and
a second semiconductor device positioned on the bottom surface of the interconnect frame alongside of the package substrate;
wherein the interconnect frame further comprises a redistribution layer and a frame construct layer;
further comprising a plurality of vias coupled to the redistribution layer, wherein the first device is coupled to the plurality of vias for connection to the redistribution layer and second semiconductor is coupled to the redistribution layer through a plurality of solder bumps;
wherein the frame construct layer further comprises a recess area, wherein some of the plurality of vias are positioned in the recess; and
the first semiconductor device is positioned in the recessed area and coupled to the vias in the recessed area.
13. The computing device of claim 12 , further comprising:
the interconnect frame forming an extension platform for the package substrate extending beyond at least a second side edge of the package substrate;
the recessed area comprising a cavity exposing the top surface of the package substrate, wherein the first semiconductor device is positioned partially over the cavity; and
a plurality of solder bumps positioned in the cavity coupling the first semiconductor device to the top surface of the package substrate.