Semiconductor device with air gaps and method of fabrication thereof

1. A method, comprising:

providing a structure having a frontside and a backside, the structure including a substrate, a first dielectric layer over the substrate, one or more semiconductor channel layers over the first dielectric layer and connecting a first source/drain (S/D) feature and a second S/D feature, and a gate structure engaging the one or more semiconductor channel layers, wherein the substrate is at the backside of the structure and the gate structure is at the frontside of the structure;

etching the substrate from the backside of the structure to form a first trench exposing the first S/D feature and a second trench exposing the second S/D feature;

forming an S/D contact in the first trench;

etching at least a portion of the first dielectric layer resulting in a portion of the S/D contact protruding from the first dielectric layer at the backside of the structure; and

depositing a seal layer over the S/D contact, wherein the seal layer caps an air gap between the gate structure and the seal layer.

2. The method of claim 1 , further comprising:

forming a dielectric liner on sidewalls of the portion of the S/D contact, wherein the seal layer is in contact with the dielectric liner.

3. The method of claim 2 , wherein the etching of at least the portion of the first dielectric layer includes completely removing the first dielectric layer prior to the forming of the dielectric liner.

4. The method of claim 2 , wherein the forming of the dielectric liner includes:

conformally depositing the dielectric liner on the backside of the structure; and

anisotropically etching the dielectric liner thereby removing the dielectric liner from a top surface of the S/D contact.

5. The method of claim 1 , further comprising:

depositing a second dielectric layer to fill the second trench, prior to the forming of the S/D contact in the first trench.

6. The method of claim 5 , further comprising:

etching the second dielectric layer to expose the second S/D feature, after the forming of the S/D contact in the first trench.

7. The method of claim 1 , further comprising:

thinning the seal layer, thereby exposing the S/D contact; and

forming a metal wiring layer at the backside of the structure, wherein the metal wiring layer is in contact with the S/D contact.

8. The method of claim 1 , wherein the depositing of the seal layer includes a plasma-enhanced chemical vapor deposition (PE-CVD) process.

9. The method of claim 1 , wherein the air gap extends vertically from a surface of the gate structure to a surface of the sealing layer for a distance ranging from about 0.5 nm to about 10 nm.

10. A method, comprising:

providing a structure having a frontside and a backside, the structure including a substrate, a semiconductor fin over the substrate, a first source/drain (S/D) feature and a second S/D feature over the semiconductor fin, a dielectric capping layer over the semiconductor fin, one or more semiconductor channel layers over the dielectric capping layer and connecting the first and second S/D features, and a gate structure engaging the one or more semiconductor channel layers, wherein the substrate is at the backside of the structure and the gate structure is at the frontside of the structure;

thinning down the structure from the backside of the structure until the semiconductor fin is exposed;

etching the semiconductor fin from the backside of the structure to form a first trench exposing the first S/D feature and a second trench exposing the second S/D feature;

depositing a dielectric layer in the second trench;

forming an S/D contact in the first trench;

recessing the dielectric capping layer from the backside of the structure, thereby exposing sidewalls of the S/D contact;

forming a dielectric liner on the sidewalls of the S/D contact;

depositing a seal layer over the S/D contact, resulting in an air gap sandwiched between the gate structure and the seal layer; and

forming a metal wiring layer over the seal layer, wherein the metal wiring layer electrically couples to the S/D contact.

11. The method of claim 10 , wherein the recessing of the dielectric capping layer exposes a surface of the gate structure, prior to the forming of the dielectric liner.

12. The method of claim 10 , further comprising:

after the forming the dielectric liner, removing the dielectric capping layer, thereby creating a gap between the dielectric liner and the gate structure.

13. The method of claim 10 , wherein the recessing of the dielectric capping layer also exposes sidewalls of the dielectric layer, and wherein the forming of the dielectric liner includes forming the dielectric liner on the sidewalls of the dielectric layer.

14. The method of claim 10 , further comprising:

etching the dielectric layer to expose a surface of the second S/D feature and sidewalls of the dielectric capping layer, prior to the forming of the dielectric liner,

wherein the forming of the dielectric liner includes forming the dielectric liner on the sidewalls of the dielectric capping layer.

15. The method of claim 14 , wherein the air gap extends vertically from the surface of the second S/D feature to a surface of the seal layer.

16. The method of claim 10 , further comprising:

thinning the seal layer to expose the S/D contact, prior to the forming of the metal wiring layer.

17. A method, comprising:

providing a structure having a frontside and a backside, the structure including a substrate, a semiconductor fin over the substrate, a source/drain (S/D) feature over the semiconductor fin, a dielectric capping layer over the semiconductor fin, one or more semiconductor channel layers over the dielectric capping layer and abutting the S/D feature, and a gate structure engaging the one or more semiconductor channel layers, wherein the substrate is at the backside of the structure and the gate structure is at the frontside of the structure;

thinning down the structure from the backside of the structure until the semiconductor fin is exposed;

etching the semiconductor fin from the backside of the structure to form a trench exposing the S/D feature;

forming an S/D contact in the trench;

recessing the dielectric capping layer from the backside of the structure, thereby exposing sidewalls of the S/D contact; and

depositing a seal layer over the S/D contact, resulting in an air gap sandwiched between the gate structure and the seal layer.

18. The method of claim 17 , further comprising:

thinning the seal layer to expose the S/D contact; and

forming a metal wiring layer over the seal layer, wherein the metal wiring layer electrically couples to the S/D contact.

19. The method of claim 17 , wherein the recessing of the dielectric capping layer fully removes the dielectric capping layer from the backside of the structure.

20. The method of claim 17 , further comprising:

after the recessing of the dielectric capping layer, depositing a dielectric liner on sidewalls of the S/D contact,

wherein after the depositing of the seal layer, a portion of the dielectric liner is laterally stacked between the S/D contact and the seal layer.