IP Library › Granted Patent US 11,456,311
Granted Patent B2
US 11,456,311 · App. 17/090,735 · Granted Sep 27, 2022

Method of manufacturing semiconductor device

Inventor: Min Young Heo (Icheon-si Gyeonggi-do, KR)
Assignee: SK hynix Inc.
H01L27/11556H01L27/11582H01L29/66666H01L29/7827
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Quick Facts
Patent No.
US 11,456,311
App. No.
17/090,735
Granted
Sep 27, 2022
Kind
B2
Abstract

The present technology provides a method of manufacturing a semiconductor device. The method includes forming a preliminary source structure, forming a stack structure on the preliminary source structure, the stack structure including a first material layer and a second material layer, forming a preliminary memory layer that penetrates the stack structure, forming a trench passing through the stack structure, forming a first buffer pattern by performing a surface treatment on a portion of the second material layer that is exposed by the trench, and forming a protective layer covering the first buffer pattern.

Claims (59)

1. A method of manufacturing a semiconductor device, the method comprising:

forming a preliminary source structure including a first source layer;

forming a stack structure on the preliminary source structure, the stack structure including a first material layer and a second material layer;

forming a preliminary memory layer that penetrates the stack structure;

forming a trench that penetrates the stack structure;

forming a first buffer pattern by performing a surface treatment on a portion of the second material layer that is exposed by the trench, wherein a portion of the second material layer remains between the first buffer pattern and the preliminary memory layer; and

forming a protective layer covering the first buffer pattern.

2. The method of claim 1 , wherein the surface treatment is an oxidation process, and

wherein the first buffer pattern includes oxide.

3. The method of claim 1 , wherein the preliminary source structure includes the first source layer that is exposed by the trench, and

the method further comprises forming a second buffer pattern by oxidizing a portion of the first source layer.

4. The method of claim 3 , wherein the protective layer covers the second buffer pattern.

5. The method of claim 1 , wherein the preliminary memory layer includes a preliminary tunnel insulating layer, a preliminary data storage layer that surrounds the preliminary tunnel insulating layer, and a preliminary blocking layer that surrounds the preliminary data storage layer, and

wherein the protective layer includes the same material as the preliminary data storage layer.

6. The method of claim 1 , wherein a distance between a sidewall of the first buffer pattern and a center of the trench is less than a distance between a sidewall of the first material layer and the center of the trench.

7. The method of claim 1 , wherein an upper surface of the first buffer pattern is in contact with a lower surface of the first material layer.

8. The method of claim 1 , further comprising:

forming a cavity by removing a source sacrificial layer of the preliminary source structure; and

forming a source structure by forming a second source layer in the cavity.

9. A method of manufacturing a semiconductor device, the method comprising:

forming a preliminary source structure;

forming a stack structure on the preliminary source structure, the stack structure including first material layers and second material layers;

forming a preliminary memory layer that penetrates the stack structure;

forming a trench that penetrates the stack structure;

forming buffer patterns overlapping the first material layers; and

forming a protective layer that covers the buffer patterns,

wherein the protective layer includes an interposed portion between the buffer patterns.

10. The method of claim 9 , wherein the interposed portion contacts an upper surface of one of the buffer patterns and a lower surface of another buffer pattern of the buffer patterns.

11. The method of claim 9 , wherein the protective layer includes a recess that is formed by recessing an inner sidewall of the protective layer.

12. The method of claim 9 , wherein the preliminary memory layer includes a preliminary tunnel insulating layer, a preliminary data storage layer that surrounds the preliminary tunnel insulating layer, and a preliminary blocking layer that surrounds the preliminary data storage layer, and

the method further comprises:

removing a portion of the preliminary source structure to expose the preliminary blocking layer;

removing a portion of the preliminary blocking layer; and

simultaneously removing a portion of the preliminary data storage layer and the protective layer.

13. The method of claim 12 , further comprising:

simultaneously removing a portion of the preliminary tunnel insulating layer and the buffer patterns.

14. The method of claim 9 , further comprising:

simultaneously removing the buffer patterns and the first material layers.

15. The method of claim 9 , further comprising:

removing the protective layer to expose the buffer patterns;

removing the buffer patterns to expose the second material layers; and

replacing the second material layers with conductive patterns.

16. A method of manufacturing a semiconductor device, the method comprising:

forming a source sacrificial layer;

forming a stack structure in which first material layers and second material layers are alternately stacked;

forming a channel structure that penetrates the stack structure;

forming a trench that penetrates the stack structure;

forming buffer patterns by performing a surface treatment on sidewalls of the first material layers that are exposed by the trench;

forming a protective layer that covers the buffer patterns in the trench;

forming a cavity by selectively removing the source sacrificial layer;

forming a source layer that is connected to the channel structure in the cavity; and

removing the second material layers through the trench.

17. The method of claim 16 , wherein the protective layer includes a first protective portion that covers the buffer patterns and a second protective portion that covers the first protective portion, and

wherein the first and second protective portions include different materials.

18. The method of claim 17 , further comprising:

forming a preliminary memory layer that includes a preliminary tunnel insulating layer, a preliminary data storage layer, and a preliminary blocking layer; and

simultaneously removing a portion of the preliminary data storage layer and the second protective portion.

19. The method of claim 17 , further comprising:

forming a preliminary memory layer that includes a preliminary tunnel insulating layer, a preliminary data storage layer, and a preliminary blocking layer; and simultaneously removing a portion of the preliminary tunnel insulating layer and the first protective portion.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 5, 2020
From: HEO, MIN YOUNG
To: SK HYNIX INC.
Reel/Frame 054290/0983 →
Priority Claims (1)
KR 10-2020-0068100 · Jun 5, 2020 · national
Continuity (1)
Related Publication 20210384209A1 · Dec 9, 2021