Memory device
A memory device includes a memory cell array configured to store data, a control circuit configured to control the memory cell array in response to a command; and a receiver configured to be placed in an active state based on a first signal, a second signal, or an operation result of an address and the command, and be enabled to receive a command or data.
1. A memory device, comprising:
a memory cell array configured to store data;
a data input and output interface to which a command, an address, and data to be written into the memory cell array are input from an external controller, and from which data read from the memory cell array is output to the external controller;
a transmitter connected to the data input and output interface and configured to be driven with an enable signal; and
a control circuit configured to cause the memory cell array to perform a read operation in response to receipt of a read command while a first control signal is being asserted and receipt of a read address subsequent to the read command while a second control signal is being asserted,
wherein the enable signal is brought into a first level upon a concurrent assertion of the first control signal and the second control signal before receipt of the read command, and is maintained at the first level at least after the read command is received, and
wherein the first level is different from a level of the enable signal after the read command is received.
2. The memory device according to claim 1 , further comprising:
a command register configured to store a command; and
an address register configured to store an address,
wherein the first control signal comprises a signal for causing the command register to store the command, and
wherein the second control signal comprises a signal for causing the address register to store the address.
3. The memory device according to claim 2 , wherein the enable signal is brought into the first level based on a first logical operation result, the first logical operation being a logical operation between a command and a second logical operation result, and the second logical operation result being a logical operation between the first control signal and the second control signal.
4. The memory device according to claim 3 , wherein the logical operation of the first logical operation result is a Reset and Set flip flop, and
wherein the logical operation of the second logical operation result is a NAND gate.
5. The memory device according to claim 1 , wherein the transmitter outputs the data read from the memory cell array via the data input and output interface.
6. The memory device according to claim 5 , wherein the data read from the memory cell array are transmitted via the data input and output interface along with a data strobe signal.
7. The memory device according to claim 6 , wherein the enable signal is brought into the first level upon toggle of a third control signal while the first control signal and the second control signal are concurrently asserted.
8. The memory device according to claim 7 , further comprising:
a command register configured to store a command; and
an address register configured to store an address,
wherein the first control signal comprises a signal for causing the command register to store a command,
wherein the second control signal comprises a signal for causing the address register to store an address, and
wherein the third control signal comprises a signal for causing the memory device to take a command or data therein.
9. The memory device according to claim 1 , wherein the control circuit performs the read operation in response to receipt of the read command and the read address subsequent thereto along with a falling edge or a rising edge of a third command signal.
10. A memory device, comprising:
a memory cell array configured to store data;
a data input and output interface to which a command, an address, and data to be written into the memory cell array are input from an external controller, and from which data read from the memory cell array is output to the external controller;
a receiver connected to the data input and output interface and configured to be driven with an enable signal; and
a control circuit configured to cause the memory cell array to perform a write operation in response to receipt of a write command while a first control signal is being asserted, receipt of a write address subsequent to the write command while a second control signal is being asserted, and receipt of the data to be written into the memory cell array subsequent to the write address while neither of the first control signal and the second control signal is being asserted,
wherein the enable signal is brought into a first level upon a concurrent assertion of the first control signal and the second control signal before receipt of the write command, and is maintained at the first level at least after the write command is received.
11. The memory device according to claim 10 , further comprising:
a command register configured to store a command; and
an address register configured to store an address,
wherein the first control signal comprises a signal for causing the command register to store the command, and
wherein the second control signal comprises a signal for causing the address register to store the address.
12. The memory device according to claim 11 , wherein the enable signal is brought into the first level based on a first logical operation result, the first logical operation being a logical operation between a command and a second logical operation result, and the second logical operation result being a logical operation between the first control signal and the second control signal.
13. The memory device according to claim 12 , wherein the logical operation of the first logical operation result is a Reset and Set flip flop, and
wherein the logical operation of the second logical operation result is a NAND gate.
14. The memory device according to claim 10 , wherein the receiver receives the data to be written into the memory cell array via the data input and output interface.
15. The memory device according to claim 14 , wherein the data to be written into the memory cell array are received via the data input and output interface along with a data strobe signal.
16. The memory device according to claim 15 , wherein the enable signal is brought into the first level upon toggle of a third control signal while the first control signal and the second control signal are concurrently asserted.
17. The memory device according to claim 16 , further comprising:
a command register configured to store a command; and
an address register configured to store an address,
wherein the first control signal comprises a signal for causing the command register to store a command,
wherein the second control signal comprises a signal for causing the address register to store an address, and
wherein the third control signal comprises a signal for causing the memory device to take a command or data therein.
18. The memory device according to claim 10 , wherein the first level is different from a level of the enable signal after the write command is received.
19. The memory device according to claim 18 , wherein the control circuit performs the write operation in response to receipt of the write command and the write address subsequent thereto along with a falling edge or a rising edge of a third command signal.
20. A memory device, comprising:
a memory cell array configured to store data;
a data input and output interface to which a command, an address, and data to be written into the memory cell array are input from an external controller, and from which data read from the memory cell array is output to the external controller;
a transmitter connected to the data input and output interface and configured to be driven with an enable signal;
a control circuit configured to cause the memory cell array to perform a read operation in response to receipt of a read command while a first control signal is being asserted and receipt of a read address subsequent to the read command while a second control signal is being asserted;
a command register configured to store a command; and
an address register configured to store an address,
wherein:
the enable signal is brought into a first level upon a concurrent assertion of the first control signal and the second control signal before receipt of the read command, and is maintained at the first level at least after the read command is received,
the first level is different from a level of the enable signal after the read command is received,
the first control signal comprises a signal for causing the command register to store a command, and
the second control signal comprises a signal for causing the address register to store an address.