IP Library › Granted Patent US 11,581,330
Granted Patent B2
US 11,581,330 · App. 17/091,668 · Granted Feb 14, 2023

Memory array and method used in forming a memory array comprising strings of memory cells

Inventors: John D. Hopkins (Meridian, ID); Jordan D. Greenlee (Boise, ID); Nancy M. Lomeli (Boise, ID); Alyssa N. Scarbrough (Boise, ID)
Assignee: Micron Technology, Inc.
H01L27/11582H01L27/1157H01L27/11519H01L27/11524H01L27/11556H01L27/11565
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Quick Facts
Patent No.
US 11,581,330
App. No.
17/091,668
Granted
Feb 14, 2023
Kind
B2
Abstract

A memory array comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Dummy pillars extend through the insulative tiers and the conductive tiers. A lowest of the conductive tiers comprises conducting material and dummy-region material that is aside and of different composition from that of the conducting material. The channel-material strings extend through the conducting material of the lowest conductive tier. The dummy pillars extend through the dummy-region material of the lowest conductive tier. Other embodiments, including method, are disclosed.

Claims (41)

1. A method used in forming a memory array comprising strings of memory cells, comprising:

forming a conductor tier comprising conductor material on a substrate;

forming a lower portion of a stack that will comprise vertically-alternating first tiers and second tiers above the conductor tier, the stack comprising laterally-spaced memory-block regions, material of the first tiers being of different composition from material of the second tiers, a lowest of the first tiers comprising:

sacrificial material; and

dummy-region material that is aside and of different composition from that of the sacrificial material;

forming the vertically-alternating first tiers and second tiers of an upper portion of the stack above the lower portion;

forming operative channel-material strings that extend through the first tiers and the second tiers in the upper portion and to the sacrificial material in the lowest first tier;

forming dummy pillars that extend through the first tiers and the second tiers in the upper portion and to the dummy-region material in the lowest first tier;

forming horizontally-elongated trenches into the stack that are individually between immediately-laterally-adjacent of the memory-block regions and extend to the sacrificial material in the lowest first tier;

isotropically etching the sacrificial material from the lowest first tier through the trenches selectively relative to the dummy-region material; and

after the etching, forming conductive material in the lowest first tier aside the dummy-region material, the conductive material directly electrically coupling together the channel material of individual of the operative channel-material strings and the conductor material of the conductor tier.

2. The method of claim 1 wherein all of the dummy-region material that is in the lowest first tier is in the memory-block regions in a finished circuitry construction.

3. The method of claim 1 wherein the dummy-region material that is in the lowest first tier comprises a line of the dummy-region material in and running centrally-longitudinally-along individual of the memory-block regions, the line being spaced laterally from lateral sides of the individual memory-block regions.

4. The method of claim 1 wherein the dummy-region material that is in the lowest first tier is in and extends laterally across all of individual of the memory-block regions aside a stair-step region of the individual memory-block regions.

5. The method of claim 1 wherein,

the dummy-region material that is in the lowest first tier comprises a line of the dummy-region material in and running centrally-longitudinally-along individual of the memory-block regions, the line being spaced laterally from lateral sides of the individual memory-block regions; and

the dummy-region material that is in the lowest first tier is in and extends laterally across all of individual of the memory-block regions aside a stair-step region of the individual memory-block regions.

6. The method of claim 1 comprising forming the operative channel-material strings and the dummy pillars to extend through the lowest first tier in the lower portion.

7. The method of claim 6 wherein the operative channel-material strings and the dummy pillars extend into the conductor material of the conductor tier.

8. The method of claim 1 comprising forming the operative channel-material strings and the dummy pillars at the same time and of the same composition relative one another.

9. The method of claim 1 wherein the sacrificial and dummy-region materials comprise polysilicon and the isotropically etching comprises use of tetramethyl ammonium hydroxide.

10. The method of claim 1 wherein the dummy-region material is formed by a process comprising:

forming a blanket layer of the sacrificial material in the lowest first tier; and

ion implanting regions of the blanket layer of the sacrificial material to form said dummy-region material.

11. The method of claim 10 wherein the ion implanting is with one of more of C, N, B, Ga, As, Sb, Bi, Li, Al, In, a Group 18 element, or a metal material.

12. The method of claim 10 wherein,

the sacrificial material comprises polysilicon or silicon nitride;

the ion implanting is with one of more of C, N, B, Ga, As, Sb, Bi, Li, Al, In, a Group 18 element, or a metal material; and

the isotropically etching comprises use of tetramethyl ammonium hydroxide or phosphoric acid.

13. The method of claim 1 wherein the dummy-region material is formed by a process comprising:

forming a blanket layer of the sacrificial material in the lowest first tier;

subtractively patterning the blanket layer of the sacrificial material to form void space therein; and

forming the dummy-region material in the void space.

14. The method of claim 1 wherein the dummy-region material is formed by a process comprising:

forming a blanket layer of the dummy-region material in the lowest first tier;

subtractively patterning the blanket layer of the dummy-region material; and

forming the sacrificial material aside the dummy-region material.

15. The method of claim 1 wherein the dummy-region material is insulative.

16. The method of claim 1 wherein the dummy-region material is conductive.

17. The method of claim 1 wherein the dummy-region material is semiconductive.

18. The method of claim 1 wherein the isotropically etching of the sacrificial material from the lowest first tier through the trenches is at a selectivity relative to the dummy-region material of at least 5:1.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 6, 2020
From: HOPKINS, JOHN D.; GREENLEE, JORDAN D.; LOMELI, NANCY M.; SCARBROUGH, ALYSSA N.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 054302/0283 →
Continuity (1)
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