Gate isolation feature and manufacturing method thereof
A semiconductor structure includes a plurality of fin structures extending along a first direction, a plurality of gate structure segments positioned along a line extending in a second direction, the second direction being orthogonal to the first direction, wherein the gate structure segments are separated by dummy fin structures. The semiconductor structure further includes a conductive layer disposed over both the gate structure segments and the dummy fin structures to electrically connect at least some of the gate structure segments, and a cut feature aligned with one of the dummy fin structures and positioned to electrically isolate gate structure segments on both sides of the one of the dummy fin structures.
1. A semiconductor structure comprising:
a plurality of fin structures extending along a first direction over a substrate;
a plurality of gate structure segments positioned along a line extending in a second direction, the second direction being orthogonal to the first direction, wherein the gate structure segments are separated by dummy fin structures, wherein the dummy fin structures include a first dummy fin structure having a first sidewall, a second sidewall that opposes the first sidewall and a topmost surface extending from the first sidewall to the second sidewall;
a conductive layer disposed over both the gate structure segments and the dummy fin structures to electrically connect at least some of the gate structure segments; and
a cut feature aligned with one of the dummy fin structures and positioned to electrically isolate gate structure segments on both sides of the one of the dummy fin structures, wherein the cut feature physically contacts the first sidewall, the second sidewall and the topmost surface of the first dummy fin structure.
2. The semiconductor structure of claim 1 , wherein the first dummy fin structure comprises a high-k dielectric material disposed on an oxide material.
3. The semiconductor structure of claim 2 , wherein a bottom of the high-k dielectric material is higher than a top of channel portions of the plurality of fin structures.
4. The semiconductor structure of claim 1 , wherein the first dummy fin structure includes an oxide material and a dielectric sheet layer on both sides of the first dummy fin structure.
5. The semiconductor structure of claim 1 , wherein a top of the dummy fin structures is higher than a top of the plurality of gate structure segments.
6. The semiconductor structure of claim 5 , wherein the top of the dummy fin structures is higher than the top of the plurality of gate structure segments by about 5-10 nanometers.
7. The semiconductor structure of claim 1 , wherein the conductive layer comprises tungsten.
8. The semiconductor structure of claim 1 , wherein the fin structures comprise stacking channel structures.
9. The semiconductor structure of claim 1 , wherein the cut feature extends below a top surface of the gate structure segments by less than two nanometers.
10. A semiconductor structure comprising:
a first gate structure segment and a second gate structure segment extending along a line in a first direction and separated by a first dummy fin structure extending in a second direction orthogonal to the first direction;
a third gate structure segment separated from the second gate structure segment by a second dummy fin structure extending along the second direction, wherein the second dummy fin structure has a first sidewall, a second sidewall that opposes the first sidewall and a topmost surface extending from the first sidewall to the second sidewall;
a conductive layer connecting the first gate structure segment and the second gate structure segment; and
a cut feature positioned above the second dummy fin structure and isolating the second gate structure segment from the third gate structure segment, wherein the cut feature physically contacts the first sidewall, the second sidewall and the topmost surface of the second dummy fin structure.
11. The semiconductor structure of claim 10 , further comprising, channel structures extending through the first, second, and third gate structure segments.
12. The semiconductor structure of claim 11 , wherein the channel structures comprise nanowires.
13. The semiconductor structure of claim 11 , wherein the channel structures comprise nanosheets.
14. The semiconductor structure of claim 11 , further comprising a self-aligned capping layer positioned above the conductive layer.
15. The semiconductor structure of claim 10 , wherein the cut feature comprises a same material as the self-aligned capping layer.
16. The semiconductor structure of claim 10 , wherein both the first dummy fin structure and the second dummy fin structure comprise:
an center portion including a first dielectric material;
a sheet portion including a second dielectric material on sidewalls of the center portion; and
a high-k dielectric material on top of the center portion.
17. The semiconductor structure of claim 16 , wherein a top surface of the high-k portion is positioned above a top surface of the first, second, and third gate structure segments.
18. A device comprising:
a first dummy fin structure disposed over a substrate, the first dummy fin structure having a topmost surface facing away from the substrate;
a first plurality of first semiconductor layers disposed over the substrate;
a first metal gate structure wrapping around the first plurality of first semiconductor layers and interfacing with the first dummy fin structure;
a second plurality of second semiconductor layers disposed over the substrate;
a second metal gate structure wrapping around the second plurality of second semiconductor layers and interfacing with the first dummy fin structure;
a conductive layer including a first portion and a second portion, the first portion of the conductive layer interfacing with the first metal gate structure and the first dummy fin structure, the second portion of the conductive layer interfacing with the second metal gate structure and the first dummy fin structure; and
a cut feature interfacing with the first dummy fin structure, the first portion of the conductive layer and the second portion of the conductive layer such that the cut feature isolates the first metal gate structure from the second metal gate structure, wherein the cut feature, the first portion of the conductive layer and the second portion of the conductive layer interface with the topmost surface of the first dummy fin structure.
19. The device of claim 18 , wherein the first dummy fin structure is formed of a plurality of dielectric material layers including at least an oxide layer and a high-k dielectric layer.
20. The device of claim 18 , wherein the first dummy fin structure extends to a greater height above the substrate than either of the first metal gate structure and the second metal gate structure.