Error correcting code poisoning for memory devices and associated methods and systems
Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory devices are configured to poison data based on an indication provided by a host device coupled with the memory devices. The indication may include which one or more bits to poison (invert) at which stages of performing write or read operations. In some embodiments, the memory device may invert one or more bits according to the indication and then correct one or more errors associated with inverting the one or more bit to verify its on-die ECC functionality. In some embodiments, the memory device may provide the host device with poisoned data including one or more bits inverted according to the indication such that the host device may test system-level ECC functionality using the poisoned data.
1. A method, comprising:
receiving, at a memory device, a command from a host device coupled with the memory device, the command directed to a first data set;
generating, from the first data set, a second data set including one or more bits inverted based on one or more bit locations indicated to the memory device;
detecting one or more errors in the second data set based, at least in part, on the one or more bits inverted;
correcting the one or more errors in the second data set to generate a third data set comprising bits that match the first data set; and
transmitting, to the host device, the third data set generated from the second data set and comprising the bits that match the first data set,
wherein one or more registers of the memory device are programmed by the host device to include the one or more bit locations, prior to receiving the command.
2. The method of claim 1 , wherein the one or more bit locations are indicated to the memory device through one or more commands to program the one or more registers of the memory device transmitted from the host device to the memory device, prior to receiving the command.
3. The method of claim 1 , wherein the command corresponds to a write command providing the first data set, and generating the second data set from the first data set further comprises:
calculating error correcting code (ECC) check bits using the first data set, wherein the second data set includes the first data set and the ECC check bits; and
inverting the one or more bits of the second data set corresponding to the one or more bit locations.
4. The method of claim 3 , further comprising:
writing the second data set to a memory array of the memory device, the write command including an address of the memory array to write the second data set.
5. The method of claim 4 , further comprising:
receiving a read command from the host device, the read command including the address; and
reading, in response to receiving the read command, the second data set from the memory array, wherein detecting the one or more errors in the second data set corresponds to detecting the one or more errors in the second data set read from the memory array.
6. The method of claim 1 , wherein the command corresponds to a read command reading the first data set from a memory array of the memory device, and generating the second data set from the first data set further comprises:
reading the first data set and a first group of ECC check bits from an address of the memory array included in the read command, the first group of ECC check bits calculated using the first data set; and
inverting the one or more bits of the first data set and the first group of ECC check bits read from the memory array, the one or more bits corresponding to the one or more bit locations, wherein the second data set includes the first data set and the first group of ECC check bits with the one or more bits inverted.
7. The method of claim 6 , further comprising:
calculating a second group of ECC check bits using the second data set; and
comparing the first group of ECC check bits with the second group of ECC check bits.
8. The method of claim 7 , wherein detecting the one or more errors in the second data set is based, at least in part, on comparing the first group of ECC check bits with the second group of ECC check bits.
9. A method, comprising:
receiving, at a memory device, a command from a host device coupled with the memory device, the command directed to a first data set;
inverting one or more bits of the first data set based on one or more bit locations indicated to the memory device by the host device using one or more registers of the memory device, one or more commands to program the one or more registers transmitted to the memory device, or both; and
transmitting the first data set with the one or more bits inverted to the host device.
10. The method of claim 9 , wherein the command corresponds to a write command providing the first data set, the method further comprising:
calculating a group of error correcting code (ECC) check bits using the first data set with the one or more bits inverted; and
writing the first data set with the one or more bits inverted and the group of ECC check bits to an address of a memory array of the memory device, the write command including the address.
11. The method of claim 10 , further comprising:
receiving, after writing the first data set with the one or more bits inverted to the address, a read command from the host device, the read command including the address; and
reading, in response to receiving the read command, the first data set with the one or more bits inverted from the memory array, wherein transmitting the first data set with the one or more bits inverted corresponds to transmitting the first data set with the one or more bits inverted read from the memory array.
12. The method of claim 11 , wherein the group of ECC check bits is a first group of ECC check bits, the method further comprising:
calculating a second group of ECC check bits using the first data set with the one or more bits inverted read from the memory array; and
comparing the first group of ECC check bits and the second group of ECC check bits, prior to transmitting the first data set with the one or more bits inverted to the host device.
13. The method of claim 9 , wherein the command corresponds to a read command reading the first data set from a memory array of the memory device, the method further comprising:
reading the first data set and a first group of ECC check bits from an address of the memory array included in the read command, the first group of ECC check bits calculated using the first data set;
calculating a second group of ECC check bits using the first data set read from the memory array; and
comparing the first group of ECC check bits with the second group of ECC check bits.
14. The method of claim 13 , wherein inverting the one or more bits of the first data set corresponds to inverting the one or more bits of the first data set read from the memory array, after comparing the first group of ECC check bits with the second group of ECC check bits.
15. An apparatus, comprising:
a memory array;
peripheral circuitry coupled with the memory array, the peripheral circuitry configured to:
receive a command from a host device coupled with the apparatus, the command directed to a first data set;
generate, from the first data set, a second data set including one or more bits inverted based on one or more bit locations indicated to the apparatus;
detect one or more errors in the second data set based, at least in part, on the one or more bits inverted;
correct the one or more errors in the second data set to generate a third data set comprising bits that match the first data set; and
transmitting, to the host device, the third data set generated from the second data set and comprising the bits that match the first data set; and
one or more registers configured to include the one or more bit locations based, at least in part, on an indication from the host device.
16. The apparatus of claim 15 , further comprising:
a command decoder configured to determine the one or more bit locations based, at least in part, on one or more commands to program the one or more registers of the apparatus transmitted from the host device.
17. The apparatus of claim 15 , wherein the peripheral circuitry is further configured to:
calculate error correcting code (ECC) check bits using the first data set provided with a write command from the host device, wherein the second data set includes the first data set and the ECC check bits; and
invert the one or more bits of the second data set corresponding to the one or more bit locations.
18. The apparatus of claim 15 , wherein the peripheral circuitry is further configured to:
read the first data set and a first group of ECC check bits from an address of the memory array included in a read command from the host device, the first group of ECC check bits calculated using the first data set; and
invert the one or more bits of the first data set and the first group of ECC check bits read from the memory array, the one or more bits corresponding to the one or more bit locations, wherein the second data set includes the first data set and the first group of ECC check bits with the one or more bits inverted.