High-density neuromorphic computing element
A neuromorphic device for the analog computation of a linear combination of input signals, for use, for example, in an artificial neuron. The neuromorphic device provides non-volatile programming of the weights, and fast evaluation and programming, and is suitable for fabrication at high density as part of a plurality of neuromorphic devices. The neuromorphic device is implemented as a vertical stack of flash-like cells with a common control gate contact and individually contacted source-drain (SD) regions. The vertical stacking of the cells enables efficient use of layout resources.
1. A method for fabricating a neuromorphic device, the method comprising:
forming, on a substrate, a first floating-gate transistor, the first floating-gate transistor having:
a channel;
a floating gate; and
a control gate; and
forming a second floating-gate transistor, vertically stacked on the first floating-gate transistor in a stacking direction, the second floating-gate transistor having:
a channel;
a floating gate; and
a control gate directly connected to the control gate of the first floating-gate transistor,
the forming of the second floating-gate transistor and of the first floating-gate transistor comprising:
forming a gate contact connected to:
the control gate of the first floating-gate transistor; and
the control gate of the second floating-gate transistor;
forming a first source-drain contact connected to a first end of the channel of the first floating-gate transistor;
forming a second source-drain contact connected to a second end of the channel of the first floating-gate transistor and to a first end of the channel of the second floating-gate transistor; and
forming a third source-drain contact connected to a second end of the channel of the second floating-gate transistor,
wherein the forming of the second source-drain contact includes forming a portion of the second source-drain contact to extend between the floating gate of the first floating-gate transistor and the floating gate of the second floating-gate transistor, such that the floating gate of the first floating-gate transistor, the portion of the second source-drain contact, and the floating gate of the second floating-gate transistor overlap with each other in the stacking direction.
2. The method of claim 1 , wherein the forming of the gate contact comprises forming a gate contact opening penetrating:
a horizontal portion of the first source-drain contact; and
a horizontal portion of the second source-drain contact.
3. The method of claim 1 , wherein the forming of the gate contact further comprises:
forming an internal sidewall spacer in the gate contact opening, to insulate the gate contact from the horizontal portion of the first source-drain contact; and
forming an internal sidewall spacer in the gate contact opening, to insulate the gate contact from the horizontal portion of the second source-drain contact.
4. The method of claim 1 , wherein the forming of the gate contact further comprises filling the gate contact opening with contact metal.
5. The method of claim 1 , wherein the forming of the first source-drain contact and the first source-drain contact comprises:
forming a first source-drain contact opening extending to the horizontal portion of the first source-drain contact;
forming a second source-drain contact opening extending to the horizontal portion of the second source-drain contact; and
filling the first source-drain contact opening and the second source-drain contact opening with contact metal.