MIS contact structure with metal oxide conductor
An electrical contact structure (an MIS contact) includes one or more conductors (M-Layer), a semiconductor (S-Layer), and an interfacial dielectric layer (I-Layer) of less than 4 nm thickness disposed between and in contact with both the M-Layer and the S-Layer. The I-Layer is an oxide of a metal or a semiconductor. The conductor of the M-Layer that is adjacent to and in direct contact with the I-Layer is a metal oxide that is electrically conductive, chemically stable and unreactive at its interface with the I-Layer at temperatures up to 450° C. The electrical contact structure has a specific contact resistivity of less than or equal to approximately 10 −5 -10 −7 Ω-cm 2 when the doping in the semiconductor adjacent the MIS contact is greater than approximately 2×10 19 cm −3 and less than approximately 10 −8 Ω-cm 2 when the doping in the semiconductor adjacent the MIS contact is greater than approximately 10 20 cm −3 .
1. A metal-insulator-semiconductor electrical contact, comprising a conductor including one of: WO 2 , (Nb,Sr)TiO 3 , (Ba,Sr)TiO 3 , SrRuO 3 , MoO 2 , OsO 2 , RhO 2 , RuO 2 , IrO 2 , ReO 3 , ReO 2 , LaCuO 3 , Ti 2 O 3 , TiO, V 2 O 3 , VO, Fe 3 O 4 , ZnO, indium tin oxide (ITO), aluminum-doped zinc-oxide (AZO), InSnO, and CrO 2 , or any of their doped or non-stochiometric variants; a semiconductor layer; and an interfacial dielectric layer of 0.2 nm to 10 nm thickness disposed between and in contact with both the conductor and the semiconductor layer, the interfacial dielectric layer comprising a plurality of oxide layers including at least one of (i) a metal oxide including one of: WO 3 , TiO 2 , MgO, Al 2 O 3 , HfO 2 , ZrO 2 , Ta 2 O 5 , V 2 O 5 , BaZrO 3 , La 2 O 3 , Y 2 O 3 , HfSiO 4 , ZrSiO 4 , CoO, NiO, GaO, SrTiO 3 , (Ba,Sr)TiO 3 , and ZnO, (ii) an oxide of silicon, or (iii) an oxide of germanium.
2. A method of manufacturing a metal-insulator-semiconductor electrical contact, comprising:
forming an n-type doped region of a semiconductor layer,
depositing a layer of an insulating material over the n-type doped region of the semiconductor layer;
defining a contact window and etching a hole through the layer of the insulating material to expose a surface of the n-type doped region of the semiconductor layer;
cleaning the exposed surface of the n-type doped region of the semiconductor layer;
forming a first layer of a first metal oxide on the exposed surface of the n-type doped region of the semiconductor layer;
depositing a second layer of a second metal oxide different than the first metal oxide and that is electrically conductive over the first layer of the first metal oxide;
depositing a layer of an adhesion or barrier metal and filling the hole with a bulk metal to form a metal plug.
3. A method of manufacturing a metal-insulator-semiconductor electrical contact, comprising:
forming an n-type doped region of a semiconductor layer,
depositing a layer of an insulating material over the n-type doped region of the semiconductor layer;
defining a contact window and etching a hole through the layer of insulating material to expose a surface of the n-type doped region of the semiconductor layer;
cleaning the exposed surface of the n-type doped region of the semiconductor layer;
forming a first layer of a first metal oxide on the exposed surface of the n-type doped semiconductor region of the semiconductor layer;
depositing a second layer of a second metal oxide different than the first metal oxide and that is electrically conductive over the first layer of the first metal oxide;
depositing a layer of tungsten and filling the hole with tungsten to form a tungsten plug.
4. The method of claim 2 wherein the first layer of the first metal oxide is one of: TiO 2 , MgO, Al 2 O 3 , HfO 2 , ZrO 2 , Ta 2 O 5 , V 2 O 5 , BaZrO 3 , La 2 O 3 , Y 2 O 3 , HfSiO 4 , ZrSiO 4 , CoO, NiO, SrTiO 3 or (Ba,Sr)TiO 3 , non-conducting ZnO, MnO, or any of their non-stochiometric variants.
5. The method of claim 2 wherein the second layer of the second metal oxide is one of: WO 2 , (Nb,Sr)TiO 3 , (Ba,Sr)TiO 3 , SrRuO 3 , MoO 2 , OsO 2 , RhO 2 , RuO 2 , IrO 2 , ReO 3 , ReO 2 , LaCuO 3 , Ti 2 O 3 , TiO, V 2 O 3 , VO, Fe 3 O 4 , ZnO, indium tin oxide (ITO), aluminum-doped zinc-oxide (AZO), InSnO, CrO 2 , or any of their non-stochiometric variants.
6. The method of claim 3 wherein the first layer of the first metal oxide is one of: TiO 2 , MgO, Al 2 O 3 , HfO 2 , ZrO 2 , Ta 2 O 5 , V 2 O 5 , BaZrO 3 , La 2 O 3 , Y 2 O 3 , HfSiO 4 , ZrSiO 4 , CoO, NiO, SrTiO 3 or (Ba,Sr)TiO 3 , non-conducting ZnO, MnO, or any of their non-stochiometric variants.
7. The method of claim 3 wherein the second layer of the second metal oxide is one of: WO 2 , (Nb,Sr)TiO 3 , (Ba,Sr)TiO 3 , SrRuO 3 , MoO 2 , OsO 2 , RhO 2 , RuO 2 , IrO 2 , ReO 3 , ReO 2 , LaCuO 3 , Ti 2 O 3 , TiO, V 2 O 3 , VO, Fe 3 O 4 , ZnO, indium tin oxide (ITO), aluminum-doped zinc-oxide (AZO), InSnO, CrO 2 , or any of their non-stochiometric variants.
8. The method of claim 2 , wherein the second layer of the second metal oxide is between 0.5 nm and 3.0 nm thick.
9. The method of claim 3 , wherein the second layer of the second metal oxide is between 0.5 nm and 3.0 nm thick.
10. The method of claim 2 , wherein the first layer of the first metal oxide is 0.2 nm-10 nm thick.
11. The method of claim 2 , wherein the first layer of the first metal oxide is 0.2 nm-5 nm thick.
12. The method of claim 2 , wherein the first layer of the first metal oxide is 0.2 nm-1.0 nm thick.
13. The method of claim 3 , wherein the first layer of the first metal oxide is 0.2 nm-10 nm thick.
14. The method of claim 3 , wherein the first layer of the first metal oxide is 0.2 nm-5 nm thick.
15. The method of claim 3 , wherein the first layer of the first metal oxide is 0.2 nm-1.0 nm thick.
16. The method of claim 2 , wherein the bulk metal is tungsten.
17. The method of claim 2 , wherein the semiconductor layer is one of: Si; Ge; an alloy of Si and Ge; an alloy of Ge and Sn; an alloy of Ge, Sn, and Si; SiC; GaN; InGaN; GaAs; InAs; InGaAs alloy; GaSb; InSb; terniary or quarterniary compound semiconductors, graphene, silicene, germanene, phosphorene, monolayer molybdenum disulfide, or carbon nanotubes.
18. The method of claim 3 , wherein the semiconductor layer is one of: Si; Ge; an alloy of Si and Ge; an alloy of Ge and Sn; an alloy of Ge, Sn, and Si; SiC; GaN; InGaN; GaAs; InAs; InGaAs alloy; GaSb; InSb; terniary or quarterniary compound semiconductors, graphene, silicene, germanene, phosphorene, monolayer molybdenum disulfide, or carbon nanotubes.