IP Library Assignment 069681/0837
Patent Assignment
Reel/Frame 069681/0837

Assignment of Assignor's Interest

Recorded: 2024-12-26 Pages: 13
Assignor
ACORN SEMI, LLC
Executed: 2024-12-26
Assignee
OAK IP, LLC
812 W. MCDERMOTT DR. #1026, ALLEN, TEXAS, 75013
Covered Properties (36)
Method for Depinning the Fermi Level of a Semiconductor at an Electrical Junction and Devices Incorporating Such Junctions
Patent: 7,084,423 →
Application: 10/217,758 →
Publication: US 2004/0026687
Method for Depinning the Fermi Level of a Semiconductor at an Electrical Junction and Devices Incorporating Such Junctions
Patent: 7,462,860 →
Application: 11/181,217 →
Publication: US 2005/0247956
Method for Depinning the Fermi Level of a Semiconductor at an Electrical Junction and Devices Incorporating Such Junctions
Patent: 7,884,003 →
Application: 12/197,996 →
Publication: US 2009/0104770
Method for Depinning the Fermi Level of a Semiconductor at an Electrical Junction and Devices Incorporating Such Junctions
Patent: 8,431,469 →
Application: 13/022,522 →
Publication: US 2011/0169124
Method for Depinning the Fermi Level of a Semiconductor at an Electrical Junction and Devices Incorporating Such Junctions
Patent: 9,209,261 →
Application: 14/743,916 →
Publication: US 2015/0287800
Method for Depinning the Fermi Level of a Semiconductor at an Electrical Junction and Devices Incorporating Such Junctions
Patent: 9,425,277 →
Application: 13/552,556 →
Publication: US 2012/0280294
Method for Depinning the Fermi Level of a Semiconductor at an Electrical Junction and Devices Incorporating Such Junctions
Patent: 9,812,542 →
Application: 15/251,210 →
Publication: US 2016/0372564
Method for Depinning the Fermi Level of a Semiconductor at an Electrical Junction and Devices Incorporating Such Junctions
Application: 15/981,594 →
Publication: US 2018/0269298
Method for Depinning the Fermi Level of a Semiconductor at an Electrical Junction and Devices Incorporating Such Junctions
Application: 15/728,002 →
Publication: US 2018/0033862
Method for Depinning the Fermi Level of a Semiconductor at an Electrical Junction and Devices Incorporating Such Junctions
Application: 17/304,108 →
Publication: US 2021/0305392
Method for Depinning the Fermi Level of a Semiconductor at an Electrical Junction and Devices Incorporating Such Junctions
Application: 15/929,592 →
Publication: US 2020/0273960
Method for Depinning the Fermi Level of a Semiconductor at an Electrical Junction and Devices Incorporating Such Junctions
Application: 15/929,593 →
Publication: US 2020/0273961
Method for Depinning the Fermi Level of a Semiconductor at an Electrical Junction and Devices Incorporating Such Junctions
Application: 16/847,878 →
Publication: US 2020/0243662
Method for Depinning the Fermi Level of a Semiconductor at an Electrical Junction and Devices Incorporating Such Junctions
Application: 16/506,022 →
Publication: US 2019/0334006
Method for Depinning the Fermi Level of a Semiconductor at an Electrical Junction and Devices Incorporating Such Junctions
Patent: 8,766,336 →
Application: 13/687,907 →
Publication: US 2013/0119446
Method for Depinning the Fermi Level of a Semiconductor at an Electrical Junction and Devices Incorporating Such Junctions
Patent: 9,461,167 →
Application: 15/048,893 →
Publication: US 2016/0172492
Method for Depinning the Fermi Level of a Semiconductor at an Electrical Junction and Devices Incorporating Such Junctions
Patent: 9,905,691 →
Application: 15/048,877 →
Publication: US 2016/0172491
Method for Depinning the Fermi Level of a Semiconductor at an Electrical Junction and Devices Incorporating Such Junctions
Application: 15/877,837 →
Publication: US 2018/0166552
Insulated Gate Field Effect Transistor Having Passivated Schottky Barriers to the Channel
Patent: 6,833,556 →
Application: 10/342,576 →
Publication: US 2004/0026736
Insulated Gate Field Effect Transistor Having Passivated Schottky Barriers to the Channel
Patent: 7,112,478 →
Application: 10/754,966 →
Publication: US 2004/0142524
Insulated Gate Field Effect Transistor Having Passivated Schottky Barriers to the Channel
Patent: 7,883,980 →
Application: 11/403,185 →
Publication: US 2007/0026591
Insulated Gate Field Effect Transistor Having Passivated Schottky Barriers to the Channel
Patent: 8,377,767 →
Application: 13/022,559 →
Publication: US 2011/0210376
Insulated Gate Field Effect Transistor Having Passivated Schottky Barriers to the Channel
Patent: 8,916,437 →
Application: 13/757,597 →
Publication: US 2013/0140629
Insulated Gate Field Effect Transistor Having Passivated Schottky Barriers to the Channel
Patent: 9,583,614 →
Application: 14/298,810 →
Publication: US 2014/0284666
Insulated Gate Field Effect Transistor Having Passivated Schottky Barriers to the Channel
Application: 15/418,360 →
Publication: US 2017/0133476
Transistor with Workfunction-Induced Charge Layer
Patent: 6,891,234 →
Application: 10/832,576 →
Insulated Gate Field-Effect Transistor Having Iii-Vi Source/Drain Layer(S)
Patent: 7,382,021 →
Application: 11/010,048 →
Publication: US 2005/0104137
Method for Depinning the Fermi Level of a Semiconductor at an Electrical Junction and Devices Incorporating Such Junctions
Patent: 7,176,483 →
Application: 10/753,504 →
Publication: US 2005/0093027
Process for Fabricating a Self-Aligned Deposited Source/Drain Insulated Gate Field-Effect Transistor
Patent: 7,902,029 →
Application: 11/166,286 →
Publication: US 2006/0084232
Field Effect Transistor Source or Drain with a Multi-Facet Surface
Patent: 8,212,336 →
Application: 12/549,227 →
Publication: US 2010/0065887
Mis Contact Structure with Metal Oxide Conductor
Patent: 9,620,611 →
Application: 15/186,378 →
Mis Contact Structure with Metal Oxide Conductor
Application: 15/451,164 →
Publication: US 2018/0083115
Mis Contact Structure with Metal Oxide Conductor
Application: 16/175,637 →
Publication: US 2019/0067439
Mis Contact Structure with Metal Oxide Conductor
Application: 16/742,098 →
Publication: US 2020/0152758
Mis Contact Structure with Metal Oxide Conductor
Application: 17/094,651 →
Publication: US 2023/0317814
Process for Fabricating a Self-Aligned Deposited Source/Drain Insulated Gate Field-Effect Transistor
Patent: 8,263,467 →
Application: 13/019,789 →
Publication: US 2011/0124170
Related Assignments (12)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest Aug 12, 2002
From: GRUPP, DANIEL E.; CONNELLY, DANIEL J.
To: ACORN TECHNOLOGIES, INC.
Reel/Frame 013195/0068 →
Assignment of Assignor's Interest Jan 8, 2009
From: GRUPP, DANIEL E.; CONNELLY, DANIEL J.
To: ACORN TECHNOLOGIES, INC.
Reel/Frame 022077/0447 →
Assignment of Assignor's Interest Nov 28, 2012
From: GRUPP, DANIEL E.; CONNELLY, DANIEL J.
To: ACORN TECHNOLOGIES, INC.
Reel/Frame 029367/0526 →
Assignment of Assignor's Interest Jun 22, 2015
From: GRUPP, DANIEL E.; CONNELLY, DANIEL J.
To: ACORN TECHNOLOGIES, INC.
Reel/Frame 035878/0420 →
Security Interest May 30, 2019
From: ACORN SEMI LLC
To: THE PETER NORTON LIVING TRUST DATED APRIL 28, 1989,
Reel/Frame 049320/0634 →
Assignment of Assignor's Interest Jun 26, 2019
From: ACORN TECHNOLOGIES, INC.
To: ACORN SEMI, LLC
Reel/Frame 049602/0324 →
Assignment of Assignor's Interest Sep 15, 2020
From: GRUPP, DANIEL E.; CONNELLY, DANIEL J.
To: ACORN TECHNOLOGIES, INC.
Reel/Frame 053773/0225 →
Assignment of Assignor's Interest Sep 15, 2020
From: ACORN TECHNOLOGIES, INC.
To: ACORN SEMI, LLC
Reel/Frame 053773/0306 →
Assignment of Assignor's Interest Jun 14, 2021
From: GRUPP, DANIEL E.; CONNELLY, DANIEL J.
To: ACORN TECHNOLOGIES, INC.
Reel/Frame 056538/0139 →
Assignment of Assignor's Interest Jun 14, 2021
From: ACORN TECHNOLOGIES, INC.
To: ACORN SEMI, LLC
Reel/Frame 056538/0154 →
Release of Security Interest Dec 26, 2024
From: THE PETER NORTON LIVING TRUST
To: ACORN SEMI, LLC
Reel/Frame 069792/0173 →
Release of Security Interest Dec 26, 2024
From: THE PETER NORTON LIVING TRUST
To: ACORN TECHNOLOGIES, INC.
Reel/Frame 069792/0208 →