Insulated gate field effect transistor having passivated schottky barriers to the channel
A transistor includes a semiconductor channel disposed nearby a gate and in an electrical path between a source and a drain, wherein the channel and at least one of the source or the drain are separated by an interface layer so as to form a channel-interface layer-source/drain junction in which a Fermi level of the semiconductor channel is depinned in a region near the junction and the junction has a specific contact resistance of less than approximately 1000 Ω-μm 2 . The interface layer may include a passivating material such as a nitride, a fluoride, an oxide, an oxynitride, a hydride and/or an arsenide of the semiconductor of the channel. In some cases, the interface layer consists essentially of a monolayer configured to depin the Fermi level of the semiconductor of the channel, or an amount of passivation material sufficient to terminate all or a sufficient number of dangling bonds of the semiconductor channel to achieve chemical stability of the surface. Also, the interface layer may include a separation layer of a material different than the passivating material. Where used, the separation layer has a thickness sufficient to reduce effects of metal-induced gap states in the semiconductor channel.
1. A method, comprising:
forming an insulated gate structure on a semiconductor substrate, the insulated gate structure having a conducting gate and insulating sidewalls and being separated from the substrate by a channel region under the insulated gate structure, the channel region including undercut void regions subjacent the gate oxide and extending under the insulated gate structure, said forming exposing semiconductor sidewalls of a channel under said insulated gate structure;
depositing a seed metal on the substrate in source/drain regions adjacent the channel region, the deposition being blocked from the semiconductor sidewalls of the channel by the insulated gate structure, wherein the seed metal is formed by depositing the seed metal and then removing excess seed metal from atop the insulated gate structure; and
growing at least one of (i) a source superjacent the seed metal disposed on a first side of the channel and within a first one of the undercut void regions, and (ii) a drain superjacent the seed metal disposed on a second side of the channel and within a second one of the undercut void regions, wherein at least one of the source and drain are made of a source/drain metal.
2. The method of claim 1 , wherein the seed metal contains chromium and is removed from atop the insulated gate structure using an etch with conic ammonium nitrate.
3. The method of claim 1 , wherein the channel region is funned by an isotropic etch such that semiconductor is removed where it is exposed subjacent boundaries of the insulated gate structure.
4. The method of claim 1 , wherein after forming the channel region, but prior to growing the at least one of the source and the drain, forming a passivation layer on the exposed semiconductor sidewalls of the channel.
5. The method of claim 4 , wherein the passivation layer is essentially a monolayer of covalently bonded material.
6. The method of claim 4 wherein the passivation layer has a thickness at least 0.1 nm and less than 1.0 nm.
7. The method of claim 1 , wherein after forming the channel region, but prior to growing the at least one of the source and the drain, forming passivation and separation layers on the exposed semiconductor sidewalls of the channel.
8. The method of claim 1 , wherein the seed metal contains chromium.
9. The method of claim 1 wherein the substrate includes an insulator.
10. The method of claim 1 wherein the conducting gate comprises a metal.
11. The method of claim 1 wherein the conducting gate comprises polysilicon.
12. The method of claim 1 wherein the channel region is formed using an etch that is selective to at least one crystallographic orientation of the substrate.