Insulated gate field effect transistor having passivated schottky barriers to the channel
A transistor includes a semiconductor channel disposed nearby a gate and in an electrical path between a source and a drain, wherein the channel and at least one of the source or the drain are separated by an interface layer so as to form a channel-interface layer-source/drain junction in which a Fermi level of the semiconductor channel is depinned in a region near the junction and the junction has a specific contact resistance of less than approximately 1000 Ω-μm 2 . The interface layer may include a passivating material such as a nitride, a fluoride, an oxide, an oxynitride, a hydride and/or an arsenide of the semiconductor of the channel. In some cases, the interface layer consists essentially of a monolayer configured to depin the Fermi level of the semiconductor of the channel, or an amount of passivation material sufficient to terminate all or a sufficient number of dangling bonds of the semiconductor channel to achieve chemical stability of the surface. Also, the interface layer may include a separation layer of a material different than the passivating material. Where used, the separation layer has a thickness sufficient to reduce effects of metal-induced gap states in the semiconductor channel.
1. A method of fabricating a transistor, comprising:
forming an insulated gate structure on a substrate;
forming a channel beneath the insulated gate structure, wherein the channel is formed in part, by removing a portion of the substrate that is substantially not subjacent and concealed by the gate structure;
forming a layer of arsenic on at least one exposed sidewall surface of the channel: and
forming a metal source and a metal drain terminal on a first and a second side of the channel, including on the arsenic layer.
2. The method of claim 1 , wherein removal of the portion of the substrate comprises etching a silicon on insulator that has a Si-100 orientation with tetramethylammonium hydroxide (TMAH) to form angled sidewalls that slope inward toward the gate structure.
3. A method of fabricating a transistor, comprising:
forming an insulated gate structure on a substrate;
forming a channel beneath the insulated gate structure such that the channel and the insulated gate structure define a first and a second undercut void region that extend underneath the insulated gate structure toward the channel from a first and a second side of the insulated gate structure, respectively;
forming a layer of arsenic on at least one exposed sidewall surface of the channel, and
forming a metal source and a metal drain terminal on a first and a second side of the channel, including on the arsenic layer and within the undercut void regions beneath the insulated gate structure.
4. The method of claim 3 , wherein the substrate comprises a silicon on insulator substrate.
5. The method of claim 3 , wherein the substrate comprises a silicon on sapphire substrate.
6. The method of claim 3 , wherein. the insulated gate structure comprises an aluminum gate formed on an oxide, said aluminum gate formed by depositing a layer of aluminum on the oxide, depositing a photoresist layer on the deposited aluminum layer, exposing a pattern including a width in the photoresist, removing a portion of the photoresist according to the exposed pattern, etching a portion of the deposited aluminum layer according to the patterned photoresist, and removing the remaining photoresist.
7. The method of claim 6 , wherein the insulated gate structure includes an oxide of aluminum formed on exposed portions, including a top and sides, of the aluminum gate, said oxide of aluminum formed by oxidizing the aluminum gate.
8. The method of claim 3 , wherein the channel is formed, in part, by a wet etch that is sensitive to crystal surface orientation or reactive ion etching (RIE).
9. The method of claim 3 , wherein the channel is formed, in part, by removing a portion of the channel that is subjacent and aligned with the gate structure, thereby producing the undercut void regions, said removal effected by a non-directional or isotropic wet silicon etch with tetramethylammonium hydroxide (TMAH) or an isotropic reactive ion etch (RIE).
10. The method of claim 3 wherein forming the source and drain terminals include depositing a seed metal layer anisotropically.
11. The method of claim 3 , wherein the arsenic layer comprises a monolayer.
12. The method of claim 3 , wherein the gate structure includes insulating sidewall spacers.
13. The method of claim 3 , wherein the transistor comprises an n-channel transistor.
14. A method of fabricating a transistor, comprising:
forming an insulated gate structure on a substrate;
forming a channel beneath the insulated gate structure such that the channel and the insulated gate structure define at least a first undercut void region that extends underneath the insulated gate structure toward the channel from a first side of the insulated gate structure;
forming a layer of arsenic on at least one exposed sidewall surface of the channel; and
forming a metal source and a metal drain terminal on a first and a second side of the channel, including on the arsenic layer and within the undercut void region beneath the insulated gate structure.
15. The method of claim 14 , wherein forming the source and the drain terminal comprises forming at least one metal source or metal drain terminal.
16. The method of claim 15 , wherein the at least one metal source or metal drain terminal is grown from a seed layer.
17. The method of claim 14 , wherein the arsenic layer comprises a monolayer.