Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.
1. An electrical junction, comprising an interface layer disposed between and in contact with a conductor and an n-type doped semiconductor, the interface layer comprising an element having a valence equivalent to that of arsenic and configured to reduce a height of a Schottky barrier between the conductor and the semiconductor from that which would exist at a junction between the conductor and the semiconductor without the interface layer disposed therebetween.
2. The electrical junction of claim 1 , wherein the conductor comprises a metal silicide.
3. The electrical junction of claim 1 , wherein the interface layer comprises a monolayer of an element having a valence equivalent to that of arsenic.
4. The electrical junction of claim 3 , wherein the conductor comprises a metal silicide.
5. The electrical junction of claim 1 , wherein the n-type doped semiconductor comprises n-type doped silicon.
6. The electrical junction of claim 1 , wherein the n-type doped semiconductor comprises n-type doped germanium.
7. The electrical junction of claim 1 , wherein the n-type doped semiconductor comprises a source of a transistor.
8. The electrical junction of claim 7 , wherein the n-type doped semiconductor comprises n-type doped silicon.
9. The electrical junction of claim 1 , wherein the n-type doped semiconductor comprises a drain of a transistor.
10. The electrical junction of claim 1 , wherein the electrical junction has a specific contact resistance of less than or equal to approximately 100 Ω-μm2.
11. The electrical junction of claim 1 , wherein the electrical junction has a specific contact resistance of less than or equal to approximately 10 Ω-μm2.
12. The electrical junction of claim 1 , wherein the electrical junction has a specific contact resistance of less than or equal to approximately 1 Ω-μm2.
13. A field effect transistor, comprising a source conductor, a drain conductor, a semiconductor channel region between the source conductor and the drain conductor, a gate proximate the semiconductor channel region, and an interface layer comprising an element having a valence equivalent to that of arsenic between the source conductor and the semiconductor channel region.
14. The field effect transistor of claim 13 , wherein the source conductor comprises a metal silicide.
15. The field effect transistor of claim 13 , wherein the interface layer comprises a monolayer of an element having a valence equivalent to that of arsenic.
16. The field effect transistor of claim 15 , wherein the source conductor comprises a metal silicide.
17. The field effect transistor of claim 13 , wherein the semiconductor channel region comprises silicon.
18. The field effect transistor of claim 13 , wherein the semiconductor channel region comprises silicon germanium.
19. The field effect transistor of claim 13 , wherein the semiconductor channel region comprises germanium.
20. An electrical junction, comprising an interface layer disposed between and in contact with a conductor and an n-type semiconductor, the interface layer comprising an element having a valence equivalent to that of arsenic and an oxide of titanium.