Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
An electrical device in which an interface layer comprising arsenic is disposed between and in contact with a conductor and a semiconductor. In some cases, the interface layer may be a monolayer of arsenic.
1. An electrical junction, comprising an interface layer disposed between and in contact with a conductor and a semiconductor, the interface layer comprising arsenic and configured to reduce a height of a Schottky barrier between the conductor and the semiconductor from that which would exist at a junction between the conductor and the semiconductor without the interface layer disposed therebetween, and wherein the electrical junction has a specific contact resistance of less than or equal to approximately 100 Ω-μm 2 .
2. The electrical junction of claim 1 , wherein the conductor comprises a metal silicide.
3. The electrical junction of claim 1 , wherein the interface layer comprises a monolayer of arsenic.
4. The electrical junction of claim 3 , wherein the conductor comprises a metal silicide.
5. The electrical junction of claim 1 , wherein the semiconductor comprises n-type doped silicon.
6. The electrical junction of claim 1 , wherein the semiconductor comprises n-type doped germanium.
7. The electrical junction of claim 1 , wherein the conductor comprises a source of a transistor.
8. The electrical junction of claim 1 , wherein the conductor comprises a drain of a transistor.
9. The electrical junction of claim 1 , wherein the electrical junction has a specific contact resistance of less than or equal to approximately 10 Ω-μm 2 .
10. The electrical junction of claim 1 , wherein the electrical junction has a specific contact resistance of less than or equal to approximately 1 Ω-μm 2 .
11. A field effect transistor, comprising a source, a drain, an n-type semiconductor channel region between the source and the drain, a gate proximate the semiconductor channel region, and an interface layer comprising arsenic between the source and the n-type semiconductor channel region, wherein the source comprises a material having a work function substantially equal to a conduction band energy of the semiconductor channel region.
12. The field effect transistor of claim 11 , wherein the source comprises a metal silicide.
13. The field effect transistor of claim 11 , wherein the interface layer comprises a monolayer of arsenic.
14. The field effect transistor of claim 13 , wherein the source comprises a metal silicide.
15. The field effect transistor of claim 11 , wherein the semiconductor channel region comprises silicon.
16. The field effect transistor of claim 11 , wherein the semiconductor channel region comprises silicon germanium.
17. The field effect transistor of claim 11 , wherein the semiconductor channel region comprises germanium.
18. An electrical junction, comprising an interface layer disposed between and in contact with a conductor and an a-type semiconductor, the interface layer comprising arsenic and a titanium oxide.