IP Library Granted Patent US 10,388,748
Granted Patent B2
US 10,388,748 · App. 15/728,002 · Granted Aug 20, 2019

Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions

Inventors: Daniel E. Grupp (Palo Alto, CA); Daniel J. Connelly (Redwood City, CA)
Assignee: Acorn Technologies, Inc.
H01L29/456H01L21/28537H01L29/0895H01L29/16H01L29/161H01L29/1608H01L29/45H01L29/47H01L29/66143H01L29/66643H01L29/78H01L29/7839H01L29/806H01L29/812H01L29/872H01L29/785
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Quick Facts
Patent No.
US 10,388,748
App. No.
15/728,002
Granted
Aug 20, 2019
Kind
B2
Abstract

An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.

Claims (21)

1. An electrical junction, comprising:

a semiconductor region in a substrate;

a metal electrical contact to said semiconductor region; and

a passivating dielectric tunnel barrier layer between said semiconductor region and said metal electrical contact, said semiconductor region being electrically connected to said metal electrical contact through said passivating dielectric tunnel barrier layer, wherein said passivating dielectric tunnel barrier layer is configured to increase a height of a Schottky barrier between the metal electrical contact and the semiconductor region from that which would exist at a contact junction between the metal electrical contact and the semiconductor region without the dielectric tunnel barrier layer disposed therebetween.

2. The electrical junction of claim 1 , wherein the metal electrical contact comprises one of: platinum (Pt), iridium (Ir), gold (Au), tungsten (W), nickel (Ni), molybdenum (Mo), copper (Cu), cobalt (Go), or palladium (Pd).

3. The electrical junction of claim 1 , wherein the semiconductor region comprises one of: Si, Ge, C, an alloy of Ge and Si, an alloy of Ge and C, an alloy of Si and C, and an alloy of Si, Ge, and C.

4. The electrical junction of claim 1 , wherein the semiconductor region comprises C, a crystal structure of which is one of: a diamond lattice, a fulleride or a polymer.

5. The electrical junction of claim 1 , wherein the semiconductor region comprises an n-type semiconductor and the conductor comprises one of: platinum (Pt), iridium (Ir), gold (Au), tungsten (W), nickel (Ni), molybdenum (Mo), copper (Cu), cobalt (Go), or palladium (Pd).

6. The electrical junction of claim 1 , wherein the semiconductor region comprises a p-type semiconductor.

7. The electrical junction of claim 6 , wherein the metal electrical contact comprises one of: aluminum (Al), rubidium (Rb), barium (Ba), indium (In), titanium (Ti), chromium (Cr), tantalum (Ta), cesium (Cs), magnesium (Mg), erbium (Er), ytterbium (Yb), manganese (Mn), lead (Pb), silver (Ag), yttrium (Y), and zinc (Zn).

8. An electrical junction, comprising:

a semiconductor region in a substrate;

a metal electrical contact to said semiconductor region; and

a passivating dielectric tunnel barrier layer between said semiconductor region and said metal electrical contact, said semiconductor region being electrically connected to said metal electrical contact through said passivating dielectric tunnel barrier layer,

wherein said semiconductor region and said metal electrical contact have asymmetric electrical potentials that are further apart from one another than would exist at a contact junction between the metal electrical contact and the semiconductor region without the passivating dielectric tunnel barrier layer disposed therebetween.

9. The electrical junction of claim 8 , wherein the metal electrical contact comprises one of: platinum (Pt), iridium (Ir), gold (Au), tungsten (W), nickel (Ni), molybdenum (Mo), copper (Cu), cobalt (Go), or palladium (Pd).

10. The electrical junction of claim 8 , wherein the semiconductor region comprises one of: Si, Ge, C, an alloy of Ge and Si, an alloy of Ge and C, an alloy of Si and C, and an alloy of Si, Ge, and C.

11. The electrical junction of claim 8 , wherein the semiconductor region comprises C, a crystal structure of which is one of: a diamond lattice, a fulleride or a polymer.

12. The electrical junction of claim 8 , wherein the semiconductor region comprises an n-type semiconductor and the conductor comprises one of: platinum (Pt), iridium (Ir), gold (Au), tungsten (W), nickel (Ni), molybdenum (Mo), copper (Cu), cobalt (Go), or palladium (Pd).

13. The electrical junction of claim 8 , wherein the semiconductor region comprises a p-type semiconductor.

14. The electrical junction of claim 13 , wherein the metal electrical contact comprises one of: aluminum (Al), rubidium (Rb), barium (Ba), indium (In), titanium (Ti), chromium (Cr), tantalum (Ta), cesium (Cs), magnesium (Mg), erbium (Er), ytterbium (Yb), manganese (Mn), lead (Pb), silver (Ag), yttrium (Y), and zinc (Zn).

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 26, 2024
From: ACORN SEMI, LLC
To: OAK IP, LLC
Reel/Frame 069681/0837 →
RELEASE OF SECURITY INTEREST Recorded Dec 26, 2024
From: THE PETER NORTON LIVING TRUST
To: ACORN SEMI, LLC
Reel/Frame 069792/0173 →
RELEASE OF SECURITY INTEREST Recorded Dec 26, 2024
From: THE PETER NORTON LIVING TRUST
To: ACORN TECHNOLOGIES, INC.
Reel/Frame 069792/0208 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 26, 2019
From: ACORN TECHNOLOGIES, INC.
To: ACORN SEMI, LLC
Reel/Frame 049602/0324 →
SECURITY INTEREST Recorded May 30, 2019
From: ACORN SEMI LLC
To: THE PETER NORTON LIVING TRUST DATED APRIL 28, 1989,
Reel/Frame 049320/0634 →
Continuity (8)
Continuation 15251210 · Aug 30, 2016
Continuation 15048877 · Feb 19, 2016
Continuation 13552556 · Jul 18, 2012
Continuation 13022522 · Feb 7, 2011
Division 12197996 · Aug 25, 2008
Division 11181217 · Jul 13, 2005
Continuation 10217758 · Aug 12, 2002
Related Publication 20180033862A1 · Feb 1, 2018