Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.
1. An electrical junction, comprising:
a semiconductor region in a substrate;
a metal electrical contact proximate to said semiconductor region; and
an interface layer disposed between said semiconductor region and said metal electrical contact, said interface layer including a first layer containing a passivating material and a second layer that displaces the semiconductor region from the metal electrical contact, said semiconductor region being electrically connected to said metal electrical contact through said interface layer.
2. The electrical junction of claim 1 , wherein the metal electrical contact comprises a metal silicide.
3. The electrical junction of claim 1 , wherein the semiconductor region comprises a source of a transistor.
4. The electrical junction of claim 3 , wherein the semiconductor region comprises n-type doped silicon.
5. The electrical junction of claim 1 , wherein the second layer comprises an oxide.
6. The electrical junction of claim 1 , wherein the first layer comprises a semiconductor oxide.
7. The electrical junction of claim 6 , wherein the second layer comprises an oxide.
8. An electrical junction, comprising:
a semiconductor region in a substrate;
a metal layer in electrical contact with said semiconductor region; and
an interface layer disposed between said semiconductor region and said metal layer, said interface layer including a monolayer of passivating material and configured to reduce a specific electrical contact resistance between the metal layer and the semiconductor region from that which would exist at a junction between the metal layer and the semiconductor region without the interface layer disposed between the semiconductor region and the metal layer, said semiconductor region being electrically connected to said metal layer through said interface layer.
9. The electrical junction of claim 8 , wherein the semiconductor region comprises silicon and the metal layer comprises a metal silicide.
10. The electrical junction of claim 8 , wherein the semiconductor region comprises n-type doped silicon.
11. The electrical junction of claim 8 , wherein the semiconductor region comprises a source of a transistor.
12. The electrical junction of claim 11 , wherein the semiconductor region comprises n-type doped silicon.
13. The electrical junction of claim 11 , wherein the semiconductor region comprises n-type doped silicon germanium.
14. The electrical junction of claim 8 , wherein the monolayer of passivating material comprises arsenic.
15. The electrical junction of claim 8 , wherein the monolayer of passivating material comprises an element of same valence as arsenic.
16. The electrical junction of claim 15 , wherein the monolayer of passivating material comprises nitrogen.
17. The electrical junction of claim 8 , wherein the monolayer of passivating material comprises oxygen.
18. The electrical junction of claim 8 , wherein the specific electrical contact resistance between the metal layer and the semiconductor is less than 100 Ohm-micron 2 .
19. The electrical junction of claim 8 , wherein the specific electrical contact resistance between the metal layer and the semiconductor is less than 1 Ohm-micron 2 .
20. The electrical junction of claim 8 , wherein the semiconductor region comprises n-type doped silicon germanium.