Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.
1. An electrical junction, comprising an interface layer disposed between a contact metal and a source or drain of a transistor, the source or drain of the transistor comprising a silicon-based semiconductor, and the interface layer comprising a spacer layer that is an oxide of titanium and a semiconductor oxide passivation layer, wherein the semiconductor oxide passivation layer has a thickness of less than about 1 nm.
2. The electrical junction of claim 1 , wherein the contact metal comprises one of: platinum (Pt), gold (Au), tungsten (W), nickel (Ni), molybdenum (Mo), copper (Cu), cobalt (Co), or palladium (Pd).
3. The electrical junction of claim 2 , wherein the silicon-based semiconductor comprises one of: Si, SiGe, and SiC.
4. The electrical junction of claim 1 , wherein the silicon-based semiconductor comprises an n-type semiconductor and the contact metal comprises one of: platinum (Pt), gold (Au), tungsten (W), nickel (Ni), molybdenum (Mo), copper (Cu), cobalt (Co), or palladium (Pd).
5. The electrical junction of claim 1 , wherein the semiconductor oxide passivation layer is an oxide of the silicon-based semiconductor.
6. The electrical junction of claim 5 , wherein the silicon-based semiconductor is an n-type doped semiconductor.
7. The electrical junction of claim 1 , wherein the semiconductor oxide passivation layer is an oxide of silicon.
8. The electrical junction of claim 7 , wherein the silicon-based semiconductor is an n-type doped semiconductor.
9. The electrical junction of claim 1 , wherein the silicon-based semiconductor comprises an n-type silicon, the semiconductor oxide passivation layer of the interface layer is adjacent the silicon-based semiconductor and is an oxide of silicon, and the contact metal comprises titanium.
10. The electrical junction of claim 1 , wherein the silicon-based semiconductor comprises an n-type silicon, the semiconductor oxide passivation layer of the interface layer is adjacent the silicon-based semiconductor and is an oxide of silicon.
11. The electrical junction of claim 10 , wherein the spacer layer presents a potential barrier lower than 1 eV.
12. The electrical junction of claim 1 , wherein the contact metal is titanium.
13. The electrical junction of claim 1 , wherein the passivation layer is adjacent to the source or drain of the transistor.
14. The electrical junction of claim 13 , wherein the contact metal comprises tungsten.
15. The electrical junction of claim 14 , wherein the semiconductor comprises an n-type doped semiconductor.
16. The electrical junction of claim 14 , wherein the semiconductor comprises n-type silicon.
17. The electrical junction of claim 16 , wherein the semiconductor oxide passivation layer is an oxide of silicon.
18. The electrical junction of claim 13 , wherein the contact metal comprises titanium.
19. The electrical junction of claim 18 , wherein the semiconductor comprises an n-type doped semiconductor.
20. The electrical junction of claim 18 , wherein the semiconductor comprises n-type silicon.
21. The electrical junction of claim 20 , wherein the semiconductor oxide passivation layer is an oxide of silicon.
22. An electrical junction, comprising an interface layer disposed between and in contact with a contact metal and a source or drain of a transistor, the source or drain of the transistor comprising an n-type silicon-based semiconductor, the contact metal comprising titanium, and the interface layer comprising a spacer layer that is an oxide of titanium that presents a potential barrier lower than 1 eV and a passivation layer adjacent the silicon-based semiconductor that is an oxide of silicon and has a thickness of less than about 1 nm.
23. An electrical junction, comprising an interface layer disposed between and in contact with a conductor and a source or drain of a transistor, the conductor comprising a metal silicide, the source or drain of the transistor comprising an n-type silicon-based semiconductor, and the interface layer comprising a passivation layer adjacent the silicon-based semiconductor that is an oxide of silicon, the passivation layer having a thickness of less than about 1 nm.
24. The electrical junction of claim 23 , wherein the interface layer further includes a separation layer between the contact metal and the passivation layer.
25. The electrical junction of claim 24 , wherein the interface layer has a thickness of less than 5 nm.
26. The electrical junction of claim 23 , wherein the interface layer configured to provide a specific contact resistivity of the electrical junction of less than 10 Ω−μm 2 .
27. The electrical junction of claim 26 , wherein the interface layer configured to provide a specific contact resistivity of the electrical junction of less than 1 Ω−μm 2 .
28. A field effect transistor, comprising an electrical junction that includes an interface layer disposed between and in contact with a contact metal and a source or drain of the field effect transistor, the source or drain comprising n-type silicon, the contact metal comprising titanium, the interface layer including a spacer layer that is an oxide of titanium and a passivation layer adjacent the source or drain that is an oxide of silicon, wherein the passivation layer has a thickness of less than about 1 nm and the electrical junction is operable to pass a current between the contact metal and the source or drain while presenting a specific contact resistivity of less than 10 Ω−μm 2 .