IP Library Granted Patent US 10,950,707
Granted Patent B2
US 10,950,707 · App. 15/929,593 · Granted Mar 16, 2021

Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions

Inventors: Daniel E. Grupp (Palo Alto, CA); Daniel J. Connelly (Redwood City, CA)
Assignee: Acorn Semi, LLC
H01L29/456H01L21/28537H01L29/0895H01L29/16H01L29/161H01L29/1608H01L29/45H01L29/47H01L29/66143H01L29/66643H01L29/78H01L29/7839H01L29/806H01L29/812H01L29/872H01L29/785
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Quick Facts
Patent No.
US 10,950,707
App. No.
15/929,593
Granted
Mar 16, 2021
Kind
B2
Abstract

An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.

Claims (23)

1. An electrical junction comprising an interface layer disposed between and in contact with a contact metal and a source or drain of a transistor, the source or drain comprising silicon and the interface layer configured to provide a specific contact resistivity of the electrical junction of less than 10 Ω-μm 2 and comprising a spacer layer that is an oxide of titanium and a passivating layer that is an oxide of silicon.

2. The electrical junction of claim 1 , wherein the contact metal comprises one of: platinum (Pt), gold (Au), tungsten (W), nickel (Ni), molybdenum (Mo), copper (Cu), cobalt (Co), or palladium (Pd).

3. The electrical junction of claim 1 , wherein the source or drain comprises n-type silicon and the contact metal comprises one of: platinum (Pt), gold (Au), tungsten (W), nickel (Ni), molybdenum (Mo), copper (Cu), cobalt (Co), or palladium (Pd).

4. The electrical junction of claim 1 , wherein the passivating layer has a thickness of approximately 0.1 nm to 5 nm.

5. The electrical junction of claim 4 , wherein the source or drain of the transistor comprises an n-type doped silicon source or drain of the transistor.

6. The electrical junction of claim 5 , wherein the contact metal comprises titanium.

7. The electrical junction of claim 4 , wherein the spacer layer of the interface layer presents a potential barrier lower than 1 eV.

8. The electrical junction of claim 1 , wherein the contact metal comprises titanium.

9. The electrical junction of claim 8 , wherein the passivation layer has a thickness of approximately less than 1 nm.

10. The electrical junction of claim 9 , wherein the passivation layer is adjacent the source or drain of the transistor.

11. The electrical junction of claim 1 , wherein the source or drain of the transistor comprises an n-type source or drain of the transistor, the passivation layer is adjacent the n-type source or drain of the transistor and has a thickness of approximately 0.1 nm to 5 nm, and the contact metal comprises titanium.

12. The electrical junction of claim 11 , wherein the interface layer is configured to provide a specific contact resistivity of the electrical junction of less than 1 Ω-μm 2 .

13. The electrical junction of claim 12 , wherein the passivation layer has a thickness of approximately less than 1 nm.

14. The electrical junction of claim 1 , wherein the interface layer is configured to provide a specific contact resistivity of the electrical junction of less than 1 Ω-μm 2 .

15. The electrical junction of claim 14 , wherein the passivation layer has a thickness of approximately less than 1 nm.

16. The electrical junction of claim 15 , wherein the spacer layer of the interface layer presents a potential barrier lower than 1 eV.

17. The electrical junction of claim 16 , wherein the contact metal is titanium.

18. The electrical junction of claim 1 , wherein the contact metal comprises tungsten.

19. An electrical junction comprising an interface layer disposed between and in contact with a contact metal and an n-type silicon source or drain of a transistor, the interface layer configured to provide a specific contact resistivity of the electrical junction of less than 10 Ω-μm 2 and comprising a spacer layer presenting a potential barrier lower than 1 eV and a layer having a thickness of approximately 0.1 nm to 5 nm that is an oxide of silicon.

20. The electrical junction of claim 19 , wherein the spacer layer comprises an oxide of titanium.

21. The electrical junction of claim 20 , wherein the contact metal is titanium.

22. The electrical junction of claim 21 , wherein the interface layer configured to provide a specific contact resistivity of the electrical junction of less than 1 Ω-μm 2 .

23. The electrical junction of claim 19 , wherein the interface layer configured to provide a specific contact resistivity of the electrical junction of less than 1 Ω-μm 2 .

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 26, 2024
From: ACORN SEMI, LLC
To: OAK IP, LLC
Reel/Frame 069681/0837 →
RELEASE OF SECURITY INTEREST Recorded Dec 26, 2024
From: THE PETER NORTON LIVING TRUST
To: ACORN SEMI, LLC
Reel/Frame 069792/0173 →
RELEASE OF SECURITY INTEREST Recorded Dec 26, 2024
From: THE PETER NORTON LIVING TRUST
To: ACORN TECHNOLOGIES, INC.
Reel/Frame 069792/0208 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 15, 2020
From: GRUPP, DANIEL E.; CONNELLY, DANIEL J.
To: ACORN TECHNOLOGIES, INC.
Reel/Frame 053773/0225 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 15, 2020
From: ACORN TECHNOLOGIES, INC.
To: ACORN SEMI, LLC
Reel/Frame 053773/0306 →
Continuity (11)
Continuation 16847878 · Apr 14, 2020
Continuation 16506022 · Jul 9, 2019
Continuation 15728002 · Oct 9, 2017
Continuation 15251210 · Aug 30, 2016
Continuation 15048877 · Feb 19, 2016
Continuation 13552556 · Jul 18, 2012
Continuation 13022522 · Feb 7, 2011
Division 12197996 · Aug 25, 2008
Division 11181217 · Jul 13, 2005
Continuation 10217758 · Aug 12, 2002
Related Publication 20200273961A1 · Aug 27, 2020