Semiconductor memory device
Along with the miniaturization of the semiconductor memory device, the resistor and parasitic capacitance of the wires become large, which prevents the semiconductor memory device from being speeded up. In a semiconductor memory device having a semiconductor substrate having a main surface, a first memory cell row having a plurality of first memory cells arranged in parallel to a first direction in plan view on the main surface, a first word line connected to the plurality of first memory cells, a first word line driver for changing a potential of the first word line, and a control circuit for outputting a first predecode signal to the first word line driver via the first predecode line in response to a clock signal and an address signal, a repeater is inserted between the control circuit and the first word line driver.
1. A semiconductor memory device comprising:
a semiconductor substrate having a main surface;
a first memory cell row having a plurality of first memory cells arranged in parallel to a first direction in plan view on the main surface;
a first word line connected to the plurality of first memory cells;
a first word line driver configured to change a potential of the first word line;
a control circuit configured to output a first pre-decode signal to the first word line driver via the first pre-decode line in response to a clock signal and an address signal; and
a repeater circuit inserted in the first pre-decode line between the control circuit and the first word line driver,
wherein the control circuit outputs a second pre-decode signal to a second pre-decode line different from the first pre-decode line in response to the address signal,
wherein the control circuit includes:
a first pre-decoder;
a logic circuit connected to the first pre-decode line; and
a clock driver configured to output an internal clock signal in response to an input of the clock signal,
wherein the first pre-decoder outputs an internal address signal to the logic circuit in response to the address signal, and outputs the second pre-decode signal to the second pre-decode line,
wherein the logic circuit outputs the first pre-decode signal to the first pre-decode line in response to the internal clock signal and the internal address signal,
wherein the first pre-decoder outputs a third pre-decode signal to a third pre-decode line different from the first pre-decode line and the second pre-decode line in response to the address signal, and
wherein the semiconductor memory device further includes:
a second pre-decoder connected to the second pre-decode line and the third pre-decode line and outputting a fourth pre-decode signal to a fourth pre-decode line and the first pre-decode line in response to the second pre-decode signal and the third pre-decode signal; and
a main decoder connected to the fourth pre-decode line and the first pre-decode line and outputting a fifth pre-decode signal to the first word line driver in response to the fourth pre-decode signal and the first pre-decode signal.
2. The semiconductor memory device according to claim 1 , wherein each of the plurality of first memory cells comprises a fin-type field effect transistor.
3. The semiconductor memory device according to claim 1 , further comprising:
a second memory cell row having a plurality of second memory cells arranged in an extending direction of the first memory cell row, the second memory cell row being arranged in parallel to the first direction in a second direction intersecting with the first direction in the plan view;
a second word line connected to the plurality of second memory cells; and
a second word line driver configured to change a potential of the second word line,
wherein one of the first memory cell row or the second memory cell row is selected by the address signal,
wherein the first pre-decode line transmits the first pre-decode signal to the first word line driver or the second word line driver,
wherein the repeater is inserted between the control circuit and the first word line driver, and
wherein the repeater is not inserted in a position between the control circuit and the second word line driver.
4. The semiconductor memory device according to claim 1 ,
wherein the first pre-decode line comprises:
a first portion from the repeater to the control circuit; and
a second portion from the repeater to the first word line driver, and
wherein the repeater providing, in response to the first pre-decode signal, the second portion with a second potential corresponding to a high level of the first pre-decode signal or a second potential corresponding to a low level of the first pre-decode signal.
5. The semiconductor memory device according to claim 1 , wherein the repeaters comprises an even number of CMOS inverters connected in series.
6. The semiconductor memory device according to claim 1 ,
wherein the first memory cell row is included in a memory cell array,
wherein the first word line driver is included in a peripheral region located in an extension direction of the memory cell array in the first direction in a planar view, and
wherein the semiconductor memory device further comprises:
a memory well tap region arranged in an extending direction of the memory cell array in a second direction intersecting the first direction in the plan view and supplying a well power to the first memory cell; and
a peripheral well tap region arranged in an extending direction of the memory well tap region in the second direction and supplying the well power to the first word line driver,
wherein the repeater is located in the peripheral well tap region.
7. The semiconductor memory device according to claim 1 , wherein the repeater is not inserted into the first pre-decode line.
8. The semiconductor memory device according to claim 1 , wherein the first pre-decode line comprises a first portion closer to the first pre-decoder than the repeater and a second portion closer to the first word line driver than the repeater,
wherein the second portion includes a third portion extending in a second direction intersecting the first direction in the plan view and a fourth portion extending in the second direction and different from the third portion,
wherein the third portion is connected to the main decoder, and
wherein the first portion is not connected to the main decoder.
9. The semiconductor memory device according to claim 1 , wherein the repeater is provided between the second pre-decoder and the main decoder.
10. A semiconductor memory device comprising:
a semiconductor substrate having a main surface;
a first memory cell row having a plurality of first memory cells arranged in parallel to a first direction in a plan view on the main surface;
a first word line connected to the plurality of first memory cells;
a first word line driver arranged in an extending direction of the first memory cell row in the first direction and changing a potential of the first word line;
a memory well tap region arranged in an extending direction of the first memory cell row in a second direction intersecting the first direction in the plan view, and supplying a well power to the first memory cell row;
a peripheral well tap region arranged in an extending direction of the first word line driver in the second direction and supplying a well power to the memory well tap region arranged in an extending direction of the first word line driver in the first direction, and supplying a well power to the first word line driver in the first direction; and
a control circuit having a first pre-decode signal output to the first word line driver via a first pre-decode line in response to a clock signal and an address signal,
wherein the first pre-decode line includes a first portion from the control circuit to a first repeater disposed in the peripheral well tap region, and a second portion from the first repeater to the first word line driver,
wherein the control circuit outputs a second pre-decode signal to a second pre-decode line different from the first pre-decode line in response to the address signal,
wherein the control circuit includes:
a first pre-decoder;
a logic circuit connected to the first pre-decode line; and
a clock driver for outputting an internal clock signal in response to an input of the clock signal,
wherein the first pre-decoder outputs an internal address signal to the logic circuit in response to the address signal, and outputs the second pre-decode signal to the second pre-decode line,
wherein the logic circuit outputs the first pre-decode signal to the first pre-decode line in response to the internal clock signal and the internal address signal,
wherein the first pre-decoder outputs a third pre-decode signal to a third pre-decode line different from the first pre-decode line and the second pre-decode line in response to the address signal, and
wherein the semiconductor memory device further includes:
a second pre-decode connected to the second pre-decode line and the third pre-decode line and outputting a fourth pre-decode signal to a fourth pre-decode line;
the first pre-decode line in response to the second pre-decode signal and the third pre-decode signal; and
a main decoder connected to the fourth pre-decode line and the first pre-decode line and outputting a fifth pre-decode signal to the first word line driver in response to the fourth pre-decode signal and the first pre-decode signal.
11. The semiconductor memory device according to claim 10 , further comprising:
a second memory cell row having a plurality of second memory cells arranged in the extending direction of the first memory cell row in the second direction with the memory well tap region interposed therebetween;
a second word line connected to the plurality of second memory cells; and
a second word line driver arranged in the extending direction of the second memory cell row in the first direction and varying the potential of the second word line,
wherein the control circuit outputs the first pre-decode signal to the first word line driver via the first pre-decode line in response to the clock signal and the address signal, and
wherein the second portion of the first pre-decode line includes:
the second portion from the first repeater to the first word line driver; and
a third portion from the first repeater to the second word line driver.
12. The semiconductor memory device according to claim 10 , wherein the first repeater supplies a first potential corresponding to a high level of the first pre-decode signal or a second potential corresponding to a low level of the first pre-decode signal to the second portion in response to the first pre-decode signal.
13. The semiconductor memory device according to claim 10 , wherein a second repeater is provided between the second pre-decoder and the main decoder.